### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Wed Mar 11 16:58:49 2026 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 3a6f2addcc8b48b48dc896d1482217d3
project_iteration | 8 | random_id | b8c6a05b9ec65faeb2d33a3e52056931
registration_id | b8c6a05b9ec65faeb2d33a3e52056931 | route_design | TRUE
target_device | xc7z020 | target_family | zynq
target_package | clg484 | target_speed | -1
tool_flow | Vivado

user_environment
cpu_name | AMD Ryzen 9 7945HX with Radeon Graphics | cpu_speed | 2495 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 67.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractfileview_reload=1 | addsrcwizard_specify_or_create_constraint_files=1 | basedialog_apply=1 | basedialog_cancel=29
basedialog_no=1 | basedialog_ok=61 | basedialog_yes=9 | basereporttab_rerun=1
cmdmsgdialog_messages=8 | cmdmsgdialog_ok=11 | cmdmsgdialog_open_messages_view=1 | constraintschooserpanel_create_file=1
coretreetablepanel_core_tree_table=12 | createconstraintsfilepanel_file_name=1 | createsrcfiledialog_file_name=3 | filesetpanel_file_set_panel_tree=402
flownavigatortreepanel_flow_navigator_tree=77 | fpgachooser_fpga_table=1 | hcodeeditor_search_text_combo_box=15 | hjfilechooserrecentlistpreview_recent_directories=1
ipstatussectionpanel_upgrade_selected=1 | mainmenumgr_constraints=1 | mainmenumgr_file=12 | mainmenumgr_help=2
mainmenumgr_project=7 | mainmenumgr_reports=2 | mainmenumgr_window=4 | maintoolbarmgr_run=22
mainwinmenumgr_layout=4 | mainwinmenumgr_load=1 | msgtreepanel_discard_user_created_messages=1 | msgtreepanel_message_severity=2
msgtreepanel_message_view_tree=29 | msgview_critical_warnings=1 | netlistschematicview_show_io_ports_in_this_schematic=5 | netlisttreeview_netlist_tree=1
numjobschooser_number_of_jobs=1 | openfileaction_open_directory=1 | pacommandnames_auto_connect_target=7 | pacommandnames_auto_update_hier=2
pacommandnames_fileset_window=1 | pacommandnames_open_project=5 | pacommandnames_report_ip_status=1 | pacommandnames_run_synthesis=21
pacommandnames_save_design=2 | pacommandnames_set_as_top=1 | paviews_code=1 | paviews_project_summary=6
paviews_schematic=1 | programfpgadialog_program=6 | progressdialog_cancel=3 | projecttab_reload=2
rdicommands_copy=1 | rdicommands_delete=9 | removesourcesdialog_also_delete=1 | saveprojectutils_cancel=2
saveprojectutils_save=25 | settingsprojectgeneralpage_choose_device_for_your_project=1 | signaltablepanel_signal_table=15 | simpleoutputproductdialog_close_dialog_unsaved_changes_will=1
simpleoutputproductdialog_generate_output_products_immediately=2 | srcchooserpanel_add_directories=3 | srcchooserpanel_create_file=3 | srcmenu_ip_documentation=1
srcmenu_ip_hierarchy=1 | srcmenu_refresh_hierarchy=1 | syntheticagettingstartedview_recent_projects=17

java_command_handlers
addsources=8 | autoconnecttarget=7 | coreview=4 | createblockdesign=1
customizecore=3 | editdelete=9 | launchprogramfpga=8 | openhardwaremanager=15
openproject=5 | openrecenttarget=7 | programdevice=8 | recustomizecore=3
reportipstatus=1 | runbitgen=9 | runschematic=9 | runsynthesis=22
savedesign=2 | settopnode=1 | showview=4 | timingconstraintswizard=2
toolssettings=2 | upgradeip=1 | viewlayoutcmd=1

other_data
guimode=27

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=10 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=3 | totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=3 | bufio=1 | carry4=89 | fdce=706
fdpe=186 | fdre=73 | fdse=10 | gnd=22
ibuf=8 | iddr=5 | idelayctrl=1 | idelaye2=5
lut1=95 | lut2=148 | lut3=77 | lut4=235
lut5=261 | lut6=452 | mmcme2_adv=1 | muxf7=1
obuf=7 | oddr=5 | ramb36e1=2 | vcc=18
pre_unisim_transformation
bufg=3 | bufio=1 | carry4=89 | fdce=706
fdpe=186 | fdre=73 | fdse=10 | gnd=22
ibuf=8 | iddr=5 | idelayctrl=1 | idelaye2=5
lut1=95 | lut2=148 | lut3=77 | lut4=235
lut5=261 | lut6=452 | mmcme2_adv=1 | muxf7=1
obuf=7 | oddr=5 | ramb36e1=2 | vcc=18

power_opt_design
command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 | bram_ports_newly_gated=0 | bram_ports_total=4 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=975 | srls_augmented=0
srls_newly_gated=0 | srls_total=0

ip_statistics
clk_wiz_v6_0_2_0_0/1
clkin1_period=20.000 | clkin2_period=10.0 | clock_mgr_type=NA | component_name=clk_wiz_0
core_container=NA | enable_axi=0 | feedback_source=FDBK_AUTO | feedback_type=SINGLE
iptotal=1 | manual_override=false | num_out_clk=1 | primitive=MMCM
use_dyn_phase_shift=false | use_dyn_reconfig=false | use_inclk_stopped=false | use_inclk_switchover=false
use_locked=false | use_max_i_jitter=false | use_min_o_jitter=false | use_phase_alignment=true
use_power_down=false | use_reset=false
fifo_generator_v13_2_3/1
c_add_ngc_constraint=0 | c_application_type_axis=0 | c_application_type_rach=0 | c_application_type_rdch=0
c_application_type_wach=0 | c_application_type_wdch=0 | c_application_type_wrch=0 | c_axi_addr_width=32
c_axi_aruser_width=1 | c_axi_awuser_width=1 | c_axi_buser_width=1 | c_axi_data_width=64
c_axi_id_width=1 | c_axi_len_width=8 | c_axi_lock_width=1 | c_axi_ruser_width=1
c_axi_type=1 | c_axi_wuser_width=1 | c_axis_tdata_width=8 | c_axis_tdest_width=1
c_axis_tid_width=1 | c_axis_tkeep_width=1 | c_axis_tstrb_width=1 | c_axis_tuser_width=4
c_axis_type=0 | c_common_clock=1 | c_count_type=0 | c_data_count_width=11
c_default_value=BlankString | c_din_width=32 | c_din_width_axis=1 | c_din_width_rach=32
c_din_width_rdch=64 | c_din_width_wach=1 | c_din_width_wdch=64 | c_din_width_wrch=2
c_dout_rst_val=0 | c_dout_width=32 | c_en_safety_ckt=0 | c_enable_rlocs=0
c_enable_rst_sync=1 | c_error_injection_type=0 | c_error_injection_type_axis=0 | c_error_injection_type_rach=0
c_error_injection_type_rdch=0 | c_error_injection_type_wach=0 | c_error_injection_type_wdch=0 | c_error_injection_type_wrch=0
c_family=zynq | c_full_flags_rst_val=1 | c_has_almost_empty=0 | c_has_almost_full=0
c_has_axi_aruser=0 | c_has_axi_awuser=0 | c_has_axi_buser=0 | c_has_axi_id=0
c_has_axi_rd_channel=1 | c_has_axi_ruser=0 | c_has_axi_wr_channel=1 | c_has_axi_wuser=0
c_has_axis_tdata=1 | c_has_axis_tdest=0 | c_has_axis_tid=0 | c_has_axis_tkeep=0
c_has_axis_tlast=0 | c_has_axis_tready=1 | c_has_axis_tstrb=0 | c_has_axis_tuser=1
c_has_backup=0 | c_has_data_count=0 | c_has_data_counts_axis=0 | c_has_data_counts_rach=0
c_has_data_counts_rdch=0 | c_has_data_counts_wach=0 | c_has_data_counts_wdch=0 | c_has_data_counts_wrch=0
c_has_int_clk=0 | c_has_master_ce=0 | c_has_meminit_file=0 | c_has_overflow=0
c_has_prog_flags_axis=0 | c_has_prog_flags_rach=0 | c_has_prog_flags_rdch=0 | c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 | c_has_prog_flags_wrch=0 | c_has_rd_data_count=0 | c_has_rd_rst=0
c_has_rst=1 | c_has_slave_ce=0 | c_has_srst=0 | c_has_underflow=0
c_has_valid=0 | c_has_wr_ack=0 | c_has_wr_data_count=0 | c_has_wr_rst=0
c_implementation_type=0 | c_implementation_type_axis=1 | c_implementation_type_rach=1 | c_implementation_type_rdch=1
c_implementation_type_wach=1 | c_implementation_type_wdch=1 | c_implementation_type_wrch=1 | c_init_wr_pntr_val=0
c_interface_type=0 | c_memory_type=1 | c_mif_file_name=BlankString | c_msgon_val=1
c_optimization_mode=0 | c_overflow_low=0 | c_power_saving_mode=0 | c_preload_latency=1
c_preload_regs=0 | c_prim_fifo_type=2kx18 | c_prim_fifo_type_axis=1kx18 | c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 | c_prim_fifo_type_wach=512x36 | c_prim_fifo_type_wdch=1kx36 | c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=2 | c_prog_empty_thresh_assert_val_axis=1022 | c_prog_empty_thresh_assert_val_rach=1022 | c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 | c_prog_empty_thresh_assert_val_wdch=1022 | c_prog_empty_thresh_assert_val_wrch=1022 | c_prog_empty_thresh_negate_val=3
c_prog_empty_type=0 | c_prog_empty_type_axis=0 | c_prog_empty_type_rach=0 | c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 | c_prog_empty_type_wdch=0 | c_prog_empty_type_wrch=0 | c_prog_full_thresh_assert_val=2046
c_prog_full_thresh_assert_val_axis=1023 | c_prog_full_thresh_assert_val_rach=1023 | c_prog_full_thresh_assert_val_rdch=1023 | c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 | c_prog_full_thresh_assert_val_wrch=1023 | c_prog_full_thresh_negate_val=2045 | c_prog_full_type=0
c_prog_full_type_axis=0 | c_prog_full_type_rach=0 | c_prog_full_type_rdch=0 | c_prog_full_type_wach=0
c_prog_full_type_wdch=0 | c_prog_full_type_wrch=0 | c_rach_type=0 | c_rd_data_count_width=11
c_rd_depth=2048 | c_rd_freq=1 | c_rd_pntr_width=11 | c_rdch_type=0
c_reg_slice_mode_axis=0 | c_reg_slice_mode_rach=0 | c_reg_slice_mode_rdch=0 | c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 | c_reg_slice_mode_wrch=0 | c_select_xpm=0 | c_synchronizer_stage=2
c_underflow_low=0 | c_use_common_overflow=0 | c_use_common_underflow=0 | c_use_default_settings=0
c_use_dout_rst=1 | c_use_ecc=0 | c_use_ecc_axis=0 | c_use_ecc_rach=0
c_use_ecc_rdch=0 | c_use_ecc_wach=0 | c_use_ecc_wdch=0 | c_use_ecc_wrch=0
c_use_embedded_reg=0 | c_use_fifo16_flags=0 | c_use_fwft_data_count=0 | c_use_pipeline_reg=0
c_valid_low=0 | c_wach_type=0 | c_wdch_type=0 | c_wr_ack_low=0
c_wr_data_count_width=11 | c_wr_depth=2048 | c_wr_depth_axis=1024 | c_wr_depth_rach=16
c_wr_depth_rdch=1024 | c_wr_depth_wach=16 | c_wr_depth_wdch=1024 | c_wr_depth_wrch=16
c_wr_freq=1 | c_wr_pntr_width=11 | c_wr_pntr_width_axis=10 | c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 | c_wr_pntr_width_wach=4 | c_wr_pntr_width_wdch=10 | c_wr_pntr_width_wrch=4
c_wr_response_latency=1 | c_wrch_type=0 | core_container=false | iptotal=1
x_ipcorerevision=3 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=fifo_generator
x_ipproduct=Vivado 2018.3 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=13.2
xpm_cdc_async_rst/1
core_container=NA | def_val=1'b0 | dest_sync_ff=2 | init_sync_ff=0
inv_def_val=1'b1 | iptotal=1 | rst_active_high=1 | version=0

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
check-3=1 | reqp-1839=20 | rtstat-10=1 | zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
lutar-1=1 | timing-18=11

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) | board_selection=medium (10"x10") | bram=0.000000 | clocks=0.006448
confidence_level_clock_activity=High | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium | confidence_level_overall=Medium | customer=TBD | customer_class=TBD
devstatic=0.107969 | die=xc7z020clg484-1 | dsp_output_toggle=12.500000 | dynamic=0.134837
effective_thetaja=11.5 | enable_probability=0.990000 | family=zynq | ff_toggle=12.500000
flow_state=routed | heatsink=none | i/o=0.020154 | input_toggle=12.500000
junction_temp=27.8 (C) | logic=0.001304 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 | mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 | mgtavtt_voltage=1.200000 | mgtvccaux_dynamic_current=0.000000 | mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 | mgtvccaux_voltage=1.800000 | mmcm=0.105686 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=0.242806 | output_enable=1.000000 | output_load=5.000000
output_toggle=12.500000 | package=clg484 | pct_clock_constrained=1.000000 | pct_inputs_defined=25
platform=nt64 | process=typical | ram_enable=50.000000 | ram_write=50.000000
read_saif=False | set/reset_probability=0.000000 | signal_rate=False | signals=0.001244
simulation_file=None | speedgrade=-1 | static_prob=False | temp_grade=commercial
thetajb=7.4 (C/W) | thetasa=0.0 (C/W) | toggle_rate=False | user_board_temp=25.0 (C)
user_effective_thetaja=11.5 | user_junc_temp=27.8 (C) | user_thetajb=7.4 (C/W) | user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000 | vccadc_total_current=0.020000 | vccadc_voltage=1.800000
vccaux_dynamic_current=0.061793 | vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 | vccaux_static_current=0.010589 | vccaux_total_current=0.072383 | vccaux_voltage=1.800000
vccbram_dynamic_current=0.000000 | vccbram_static_current=0.000538 | vccbram_total_current=0.000538 | vccbram_voltage=1.000000
vccint_dynamic_current=0.009996 | vccint_static_current=0.007895 | vccint_total_current=0.017891 | vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000 | vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000 | vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000 | vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco18_total_current=0.000000 | vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000 | vcco25_voltage=2.500000
vcco33_dynamic_current=0.004125 | vcco33_static_current=0.001000 | vcco33_total_current=0.005125 | vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.000000 | vcco_ddr_static_current=0.000000 | vcco_ddr_total_current=0.000000 | vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.000000 | vcco_mio0_static_current=0.000000 | vcco_mio0_total_current=0.000000 | vcco_mio0_voltage=1.800000
vcco_mio1_dynamic_current=0.000000 | vcco_mio1_static_current=0.000000 | vcco_mio1_total_current=0.000000 | vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.000000 | vccpaux_static_current=0.010330 | vccpaux_total_current=0.010330 | vccpaux_voltage=1.800000
vccpint_dynamic_current=0.000000 | vccpint_static_current=0.017181 | vccpint_total_current=0.017181 | vccpint_voltage=1.000000
vccpll_dynamic_current=0.000000 | vccpll_static_current=0.003000 | vccpll_total_current=0.003000 | vccpll_voltage=1.800000
version=2018.3

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=3 | bufgctrl_util_percentage=9.38
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=16 | bufio_fixed=1 | bufio_only_fixed=1 | bufio_only_used=1
bufio_used=1 | bufio_util_percentage=6.25 | bufmrce_available=8 | bufmrce_fixed=0
bufmrce_used=0 | bufmrce_util_percentage=0.00 | bufr_available=16 | bufr_fixed=0
bufr_used=0 | bufr_util_percentage=0.00 | mmcme2_adv_available=4 | mmcme2_adv_fixed=0
mmcme2_adv_used=1 | mmcme2_adv_util_percentage=25.00 | plle2_adv_available=4 | plle2_adv_fixed=0
plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=220 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 | block_ram_tile_fixed=0 | block_ram_tile_used=2 | block_ram_tile_util_percentage=1.43
ramb18_available=280 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=140 | ramb36_fifo_fixed=0 | ramb36_fifo_used=2 | ramb36_fifo_util_percentage=1.43
ramb36e1_only_used=2
primitives
bufg_functional_category=Clock | bufg_used=3 | bufio_functional_category=Clock | bufio_used=1
carry4_functional_category=CarryLogic | carry4_used=89 | fdce_functional_category=Flop & Latch | fdce_used=706
fdpe_functional_category=Flop & Latch | fdpe_used=186 | fdre_functional_category=Flop & Latch | fdre_used=73
fdse_functional_category=Flop & Latch | fdse_used=10 | ibuf_functional_category=IO | ibuf_used=8
iddr_functional_category=IO | iddr_used=5 | idelayctrl_functional_category=IO | idelayctrl_used=1
idelaye2_functional_category=IO | idelaye2_used=5 | lut1_functional_category=LUT | lut1_used=95
lut2_functional_category=LUT | lut2_used=148 | lut3_functional_category=LUT | lut3_used=77
lut4_functional_category=LUT | lut4_used=235 | lut5_functional_category=LUT | lut5_used=261
lut6_functional_category=LUT | lut6_used=452 | mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1
muxf7_functional_category=MuxFx | muxf7_used=1 | obuf_functional_category=IO | obuf_used=7
oddr_functional_category=IO | oddr_used=5 | ramb36e1_functional_category=Block Memory | ramb36e1_used=2
slice_logic
f7_muxes_available=26600 | f7_muxes_fixed=0 | f7_muxes_used=1 | f7_muxes_util_percentage=<0.01
f8_muxes_available=13300 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 | lut_as_logic_fixed=0 | lut_as_logic_used=1115 | lut_as_logic_util_percentage=2.10
lut_as_memory_available=17400 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=975 | register_as_flip_flop_util_percentage=0.92
register_as_latch_available=106400 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=53200 | slice_luts_fixed=0 | slice_luts_used=1115 | slice_luts_util_percentage=2.10
slice_registers_available=106400 | slice_registers_fixed=0 | slice_registers_used=975 | slice_registers_util_percentage=0.92
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=53200 | lut_as_logic_fixed=0
lut_as_logic_used=1115 | lut_as_logic_util_percentage=2.10 | lut_as_memory_available=17400 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=223 | lut_in_front_of_the_register_is_used_fixed=223 | lut_in_front_of_the_register_is_used_used=283
register_driven_from_outside_the_slice_fixed=283 | register_driven_from_outside_the_slice_used=506 | register_driven_from_within_the_slice_fixed=506 | register_driven_from_within_the_slice_used=469
slice_available=13300 | slice_fixed=0 | slice_registers_available=106400 | slice_registers_fixed=0
slice_registers_used=975 | slice_registers_util_percentage=0.92 | slice_used=386 | slice_util_percentage=2.90
slicel_fixed=0 | slicel_used=242 | slicem_fixed=0 | slicem_used=144
unique_control_sets_available=13300 | unique_control_sets_fixed=13300 | unique_control_sets_used=68 | unique_control_sets_util_percentage=0.51
using_o5_and_o6_fixed=0.51 | using_o5_and_o6_used=153 | using_o5_output_only_fixed=153 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=962
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7z020clg484-1
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=NET_TEST | -verilog_define=default::[not_specified]
usage
elapsed=00:00:20s | hls_ip=0 | memory_gain=604.914MB | memory_peak=886.188MB