### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Sat Nov 15 13:53:14 2025 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 886b3f43e167417fb943f863e40c9606
project_iteration | 15 | random_id | b8c6a05b9ec65faeb2d33a3e52056931
registration_id | b8c6a05b9ec65faeb2d33a3e52056931 | route_design | TRUE
target_device | xc7a50t | target_family | artix7
target_package | fgg484 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | AMD Ryzen 9 7945HX with Radeon Graphics | cpu_speed | 2495 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 67.000 GB | total_processors | 1

vivado_usage

gui_handlers
abstractcombinedpanel_remove_selected_elements=1 | abstractfileview_reload=1 | addedconstraintswithouttargetdialog_create_new_file=1 | addedconstraintswithouttargetdialog_select_existing_file=1
addrepositoryinfodialog_ok=2 | addsrcwizard_specify_or_create_constraint_files=1 | addsrcwizard_specify_simulation_specific_hdl_files=1 | basedialog_apply=6
basedialog_cancel=38 | basedialog_no=1 | basedialog_ok=73 | basedialog_yes=5
basereporttab_rerun=5 | closeplanner_yes=1 | cmdmsgdialog_copy_message=1 | cmdmsgdialog_messages=2
cmdmsgdialog_ok=10 | confirmsavetexteditsdialog_no=1 | constraintschooserpanel_create_file=1 | coretreetablepanel_core_tree_table=9
createconstraintsfilepanel_file_name=1 | createsrcfiledialog_file_name=4 | filesetpanel_file_set_panel_tree=170 | flownavigatortreepanel_flow_navigator_tree=107
fpgachooser_fpga_table=5 | hcodeeditor_search_text_combo_box=12 | ipstatussectionpanel_upgrade_selected=5 | mainmenumgr_checkpoint=1
mainmenumgr_constraints=1 | mainmenumgr_export=2 | mainmenumgr_file=12 | mainmenumgr_flow=2
mainmenumgr_help=2 | mainmenumgr_ip=2 | mainmenumgr_open_recent_project=2 | mainmenumgr_project=8
mainmenumgr_reports=12 | mainmenumgr_text_editor=2 | mainmenumgr_tools=4 | mainmenumgr_window=22
maintoolbarmgr_run=25 | mainwinmenumgr_layout=8 | modifiedconstraintswithouttargetdialog_update=1 | msgtreepanel_discard_user_created_messages=2
msgtreepanel_message_severity=2 | msgtreepanel_message_view_tree=9 | msgview_information_messages=2 | msgview_warning_messages=2
netlistschematicview_show_io_ports_in_this_schematic=2 | pacommandnames_auto_connect_target=11 | pacommandnames_auto_update_hier=4 | pacommandnames_core_gen=1
pacommandnames_fileset_window=3 | pacommandnames_new_project=1 | pacommandnames_open_project=3 | pacommandnames_report_ip_status=5
pacommandnames_run_implementation=1 | pacommandnames_run_synthesis=22 | pacommandnames_save_design=2 | pacommandnames_set_as_top=1
pacommandnames_simulation_live_break=8 | pacommandnames_simulation_live_run_all=8 | pacommandnames_simulation_relaunch=2 | pacommandnames_simulation_run_behavioral=9
paviews_code=2 | paviews_project_summary=12 | planaheadtab_refresh_ip_catalog=1 | programfpgadialog_program=17
progressdialog_cancel=3 | projectnamechooser_choose_project_location=1 | projectnamechooser_project_name=1 | projecttab_reload=3
rdicommands_custom_commands=3 | rdicommands_delete=7 | rdicommands_settings=1 | rdiviews_waveform_viewer=77
removesourcesdialog_also_delete=3 | saveprojectutils_cancel=2 | saveprojectutils_dont_save=1 | saveprojectutils_save=22
selectablelistpanel_selectable_list=1 | settingsdialog_project_tree=10 | settingsprojectgeneralpage_choose_device_for_your_project=4 | settingsprojectiprepositorypage_add_repository=2
settingsprojectiprepositorypage_repository_chooser=1 | signaltablepanel_signal_table=9 | simpleoutputproductdialog_close_dialog_unsaved_changes_will=2 | simpleoutputproductdialog_generate_output_products_immediately=2
simulationobjectspanel_simulation_objects_tree_table=1 | simulationscopespanel_simulate_scope_table=15 | srcchooserpanel_create_file=4 | srcmenu_ip_hierarchy=2
stalerundialog_yes=1 | syntheticagettingstartedview_recent_projects=6 | tclconsoleview_tcl_console_code_editor=1 | waveformnametree_waveform_name_tree=48

java_command_handlers
addcfgmem=1 | addsources=5 | autoconnecttarget=11 | closeproject=1
coreview=1 | customizecore=2 | editdelete=7 | launchprogramfpga=18
newproject=1 | openhardwaremanager=30 | openproject=3 | openrecenttarget=12
programdevice=18 | recustomizecore=11 | reportipstatus=5 | runbitgen=17
runschematic=4 | runsynthesis=24 | savedesign=1 | settopnode=1
showview=5 | simulationbreak=8 | simulationrelaunch=2 | simulationrun=10
simulationrunall=8 | timingconstraintswizard=1 | toolssettings=8 | unselectallcmdhandler=1
upgradeip=5 | viewtaskimplementation=1

other_data
guimode=16

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=14 | simulator_language=Mixed | srcsetcount=2 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=3 | totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=3 | fdpe=2 | fdre=145 | fdse=15
gnd=15 | ibuf=1 | lut1=4 | lut2=30
lut3=41 | lut4=31 | lut5=58 | lut6=111
mmcme2_adv=1 | obufds=4 | oserdese2=8 | vcc=11
pre_unisim_transformation
bufg=3 | fdpe=2 | fdre=145 | fdse=15
gnd=15 | ibuf=1 | lut1=4 | lut2=30
lut3=41 | lut4=31 | lut5=58 | lut6=111
mmcme2_adv=1 | obufds=4 | oserdese2=8 | vcc=11

ip_statistics
clk_wiz_v6_0_2_0_0/1
clkin1_period=20.000 | clkin2_period=10.0 | clock_mgr_type=NA | component_name=clk_wiz_0
core_container=NA | enable_axi=0 | feedback_source=FDBK_AUTO | feedback_type=SINGLE
iptotal=1 | manual_override=false | num_out_clk=2 | primitive=MMCM
use_dyn_phase_shift=false | use_dyn_reconfig=false | use_inclk_stopped=false | use_inclk_switchover=false
use_locked=false | use_max_i_jitter=false | use_min_o_jitter=false | use_phase_alignment=true
use_power_down=false | use_reset=false

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
xdcb-5=1 | xdcc-1=1 | xdcc-7=1

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | clocks=0.002144 | confidence_level_clock_activity=High
confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium | confidence_level_io_activity=High
confidence_level_overall=Medium | customer=TBD | customer_class=TBD | devstatic=0.071963
die=xc7a50tfgg484-2 | dsp_output_toggle=12.500000 | dynamic=0.246249 | effective_thetaja=2.8
enable_probability=0.990000 | family=artix7 | ff_toggle=12.500000 | flow_state=routed
heatsink=medium (Medium Profile) | i/o=0.137777 | input_toggle=12.500000 | junction_temp=25.9 (C)
logic=0.000279 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 | mmcm=0.105825 | netlist_net_matched=NA | off-chip_power=0.000000
on-chip_power=0.318212 | output_enable=1.000000 | output_load=5.000000 | output_toggle=12.500000
package=fgg484 | pct_clock_constrained=1.000000 | pct_inputs_defined=100 | platform=nt64
process=typical | ram_enable=50.000000 | ram_write=50.000000 | read_saif=False
set/reset_probability=0.000000 | signal_rate=False | signals=0.000223 | simulation_file=None
speedgrade=-2 | static_prob=False | temp_grade=commercial | thetajb=9.1 (C/W)
thetasa=4.6 (C/W) | toggle_rate=False | user_board_temp=25.0 (C) | user_effective_thetaja=2.8
user_junc_temp=25.9 (C) | user_thetajb=9.1 (C/W) | user_thetasa=4.6 (C/W) | vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 | vccadc_total_current=0.020000 | vccadc_voltage=1.800000 | vccaux_dynamic_current=0.058970
vccaux_io_dynamic_current=0.000000 | vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000
vccaux_static_current=0.012631 | vccaux_total_current=0.071601 | vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000000
vccbram_static_current=0.000165 | vccbram_total_current=0.000165 | vccbram_voltage=1.000000 | vccint_dynamic_current=0.004308
vccint_static_current=0.009762 | vccint_total_current=0.014070 | vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 | vcco12_total_current=0.000000 | vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 | vcco135_total_current=0.000000 | vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 | vcco15_total_current=0.000000 | vcco15_voltage=1.500000 | vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 | vcco18_total_current=0.000000 | vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 | vcco25_total_current=0.000000 | vcco25_voltage=2.500000 | vcco33_dynamic_current=0.041150
vcco33_static_current=0.001000 | vcco33_total_current=0.042150 | vcco33_voltage=3.300000 | version=2018.3

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=3 | bufgctrl_util_percentage=9.38
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=20 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=10 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=20 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=5 | mmcme2_adv_fixed=0 | mmcme2_adv_used=1 | mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=120 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=75 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=150 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=75 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock | bufg_used=3 | fdpe_functional_category=Flop & Latch | fdpe_used=2
fdre_functional_category=Flop & Latch | fdre_used=136 | fdse_functional_category=Flop & Latch | fdse_used=15
ibuf_functional_category=IO | ibuf_used=1 | lut1_functional_category=LUT | lut1_used=4
lut2_functional_category=LUT | lut2_used=30 | lut3_functional_category=LUT | lut3_used=32
lut4_functional_category=LUT | lut4_used=31 | lut5_functional_category=LUT | lut5_used=52
lut6_functional_category=LUT | lut6_used=93 | mmcme2_adv_functional_category=Clock | mmcme2_adv_used=1
obufds_functional_category=IO | obufds_used=4 | oserdese2_functional_category=IO | oserdese2_used=8
slice_logic
f7_muxes_available=16300 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=8150 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=32600 | lut_as_logic_fixed=0 | lut_as_logic_used=188 | lut_as_logic_util_percentage=0.58
lut_as_memory_available=9600 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=65200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=153 | register_as_flip_flop_util_percentage=0.23
register_as_latch_available=65200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=32600 | slice_luts_fixed=0 | slice_luts_used=188 | slice_luts_util_percentage=0.58
slice_registers_available=65200 | slice_registers_fixed=0 | slice_registers_used=153 | slice_registers_util_percentage=0.23
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=32600 | lut_as_logic_fixed=0
lut_as_logic_used=188 | lut_as_logic_util_percentage=0.58 | lut_as_memory_available=9600 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=25 | lut_in_front_of_the_register_is_used_fixed=25 | lut_in_front_of_the_register_is_used_used=28
register_driven_from_outside_the_slice_fixed=28 | register_driven_from_outside_the_slice_used=53 | register_driven_from_within_the_slice_fixed=53 | register_driven_from_within_the_slice_used=100
slice_available=8150 | slice_fixed=0 | slice_registers_available=65200 | slice_registers_fixed=0
slice_registers_used=153 | slice_registers_util_percentage=0.23 | slice_used=66 | slice_util_percentage=0.81
slicel_fixed=0 | slicel_used=49 | slicem_fixed=0 | slicem_used=17
unique_control_sets_available=8150 | unique_control_sets_fixed=8150 | unique_control_sets_used=4 | unique_control_sets_util_percentage=0.05
using_o5_and_o6_fixed=0.05 | using_o5_and_o6_used=54 | using_o5_output_only_fixed=54 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=134
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a50tfgg484-2
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=top | -verilog_define=default::[not_specified]
usage
elapsed=00:00:12s | hls_ip=0 | memory_gain=511.164MB | memory_peak=788.852MB

xsim
command_line_options
-sim_mode=default::behavioral | -sim_type=default::