### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Sat Nov 15 09:10:00 2025 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 83102e4b422b4cad9c1a8dfbe59df284
project_iteration | 5 | random_id | b8c6a05b9ec65faeb2d33a3e52056931
registration_id | b8c6a05b9ec65faeb2d33a3e52056931 | route_design | TRUE
target_device | xc7a50t | target_family | artix7
target_package | fgg484 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | AMD Ryzen 9 7945HX with Radeon Graphics | cpu_speed | 2495 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 67.000 GB | total_processors | 1

vivado_usage

gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 | addsrcwizard_specify_or_create_constraint_files=2 | basedialog_apply=3 | basedialog_cancel=6
basedialog_no=1 | basedialog_ok=28 | basedialog_yes=5 | basereporttab_rerun=2
cmdmsgdialog_ok=5 | constraintschooserpanel_create_file=1 | coretreetablepanel_core_tree_table=8 | createconstraintsfilepanel_file_name=1
createnewdiagramdialog_design_name=1 | createsrcfiledialog_file_name=1 | filesetpanel_file_set_panel_tree=70 | flownavigatortreepanel_flow_navigator_tree=65
fpgachooser_fpga_table=5 | hpopuptitle_close=1 | ipstatussectionpanel_upgrade_selected=3 | labtoolsmenu_active_high_button=1
labtoolsmenu_binary=1 | labtoolsmenu_led=2 | labtoolsmenu_radix=8 | labtoolsmenu_toggle_button=1
ledlowhighcolordialog_high_value_color=2 | ledlowhighcolordialog_ok=2 | mainmenumgr_checkpoint=1 | mainmenumgr_export=1
mainmenumgr_file=12 | mainmenumgr_flow=2 | mainmenumgr_ip=1 | mainmenumgr_project=5
mainmenumgr_reports=8 | mainmenumgr_text_editor=2 | mainmenumgr_window=4 | maintoolbarmgr_run=1
msgtreepanel_discard_user_created_messages=4 | msgtreepanel_message_severity=5 | msgtreepanel_message_view_tree=16 | msgview_critical_warnings=1
netlistschematicview_show_io_ports_in_this_schematic=2 | pacommandnames_auto_connect_target=7 | pacommandnames_fileset_window=1 | pacommandnames_new_project=1
pacommandnames_open_project=3 | pacommandnames_report_ip_status=3 | pacommandnames_run_synthesis=1 | pacommandnames_save_design=2
paviews_code=4 | paviews_dashboard=6 | paviews_project_summary=6 | probesview_probes_tree=2
programfpgadialog_program=9 | programfpgadialog_specify_bitstream_file=1 | projectnamechooser_choose_project_location=1 | projectnamechooser_project_name=1
projecttab_reload=5 | rdicommands_delete=2 | removesourcesdialog_also_delete=1 | saveprojectutils_save=11
settingsprojectgeneralpage_choose_device_for_your_project=3 | signaltablepanel_signal_table=4 | simpleoutputproductdialog_generate_output_products_immediately=2 | srcchooserpanel_create_file=1
syntheticagettingstartedview_recent_projects=1 | syntheticastatemonitor_cancel=1 | touchpointsurveydialog_no=1 | vioprobestreetablepanel_add_probe=2
vioprobestreetablepanel_ok=1 | vioprobestreetablepanel_vio_probes_tree_table=56

java_command_handlers
addsources=2 | autoconnecttarget=7 | coreview=3 | createblockdesign=1
customizecore=2 | editdelete=2 | launchprogramfpga=9 | newproject=1
openhardwaremanager=16 | openproject=3 | openrecenttarget=7 | programdevice=9
recustomizecore=2 | reportipstatus=3 | runbitgen=12 | runschematic=8
runsynthesis=1 | savedesign=2 | setviovaluedisplaymode=4 | setviovalueradix=1
showview=6 | toolssettings=5 | upgradeip=3

other_data
guimode=7

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=2 | export_simulation_ies=2
export_simulation_modelsim=2 | export_simulation_questa=2 | export_simulation_riviera=2 | export_simulation_vcs=2
export_simulation_xsim=2 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=1 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=2 | totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
fdre=253 | gnd=6 | ibuf=1 | lut1=1
lut2=2 | lut3=28 | lut4=12 | lut5=17
lut6=62 | obuf=2 | vcc=6
pre_unisim_transformation
fdre=253 | gnd=6 | ibuf=1 | lut1=1
lut2=2 | lut3=28 | lut4=12 | lut5=17
lut6=62 | obuf=2 | vcc=6

ip_statistics
labtools_xsdbm_v3_00_a/1
c_bscan_mode=false | c_bscan_mode_with_core=false | c_clk_input_freq_hz=300000000 | c_en_bscanid_vec=false
c_enable_clk_divider=false | c_num_bscan_master_ports=0 | c_two_prim_mode=false | c_use_ext_bscan=false
c_user_scan_chain=1 | c_xsdb_num_slaves=1 | component_name=dbg_hub_CV | core_container=NA
iptotal=1
vio/1
c_build_revision=0 | c_core_info1=0 | c_core_info2=0 | c_core_major_ver=2
c_core_minor_alpha_ver=97 | c_core_minor_ver=0 | c_core_type=2 | c_cse_drv_ver=1
c_en_probe_in_activity=1 | c_major_version=2013 | c_minor_version=1 | c_next_slave=0
c_num_probe_in=2 | c_num_probe_out=1 | c_pipe_iface=0 | c_probe_in0_width=1
c_probe_in100_width=1 | c_probe_in101_width=1 | c_probe_in102_width=1 | c_probe_in103_width=1
c_probe_in104_width=1 | c_probe_in105_width=1 | c_probe_in106_width=1 | c_probe_in107_width=1
c_probe_in108_width=1 | c_probe_in109_width=1 | c_probe_in10_width=1 | c_probe_in110_width=1
c_probe_in111_width=1 | c_probe_in112_width=1 | c_probe_in113_width=1 | c_probe_in114_width=1
c_probe_in115_width=1 | c_probe_in116_width=1 | c_probe_in117_width=1 | c_probe_in118_width=1
c_probe_in119_width=1 | c_probe_in11_width=1 | c_probe_in120_width=1 | c_probe_in121_width=1
c_probe_in122_width=1 | c_probe_in123_width=1 | c_probe_in124_width=1 | c_probe_in125_width=1
c_probe_in126_width=1 | c_probe_in127_width=1 | c_probe_in128_width=1 | c_probe_in129_width=1
c_probe_in12_width=1 | c_probe_in130_width=1 | c_probe_in131_width=1 | c_probe_in132_width=1
c_probe_in133_width=1 | c_probe_in134_width=1 | c_probe_in135_width=1 | c_probe_in136_width=1
c_probe_in137_width=1 | c_probe_in138_width=1 | c_probe_in139_width=1 | c_probe_in13_width=1
c_probe_in140_width=1 | c_probe_in141_width=1 | c_probe_in142_width=1 | c_probe_in143_width=1
c_probe_in144_width=1 | c_probe_in145_width=1 | c_probe_in146_width=1 | c_probe_in147_width=1
c_probe_in148_width=1 | c_probe_in149_width=1 | c_probe_in14_width=1 | c_probe_in150_width=1
c_probe_in151_width=1 | c_probe_in152_width=1 | c_probe_in153_width=1 | c_probe_in154_width=1
c_probe_in155_width=1 | c_probe_in156_width=1 | c_probe_in157_width=1 | c_probe_in158_width=1
c_probe_in159_width=1 | c_probe_in15_width=1 | c_probe_in160_width=1 | c_probe_in161_width=1
c_probe_in162_width=1 | c_probe_in163_width=1 | c_probe_in164_width=1 | c_probe_in165_width=1
c_probe_in166_width=1 | c_probe_in167_width=1 | c_probe_in168_width=1 | c_probe_in169_width=1
c_probe_in16_width=1 | c_probe_in170_width=1 | c_probe_in171_width=1 | c_probe_in172_width=1
c_probe_in173_width=1 | c_probe_in174_width=1 | c_probe_in175_width=1 | c_probe_in176_width=1
c_probe_in177_width=1 | c_probe_in178_width=1 | c_probe_in179_width=1 | c_probe_in17_width=1
c_probe_in180_width=1 | c_probe_in181_width=1 | c_probe_in182_width=1 | c_probe_in183_width=1
c_probe_in184_width=1 | c_probe_in185_width=1 | c_probe_in186_width=1 | c_probe_in187_width=1
c_probe_in188_width=1 | c_probe_in189_width=1 | c_probe_in18_width=1 | c_probe_in190_width=1
c_probe_in191_width=1 | c_probe_in192_width=1 | c_probe_in193_width=1 | c_probe_in194_width=1
c_probe_in195_width=1 | c_probe_in196_width=1 | c_probe_in197_width=1 | c_probe_in198_width=1
c_probe_in199_width=1 | c_probe_in19_width=1 | c_probe_in1_width=1 | c_probe_in200_width=1
c_probe_in201_width=1 | c_probe_in202_width=1 | c_probe_in203_width=1 | c_probe_in204_width=1
c_probe_in205_width=1 | c_probe_in206_width=1 | c_probe_in207_width=1 | c_probe_in208_width=1
c_probe_in209_width=1 | c_probe_in20_width=1 | c_probe_in210_width=1 | c_probe_in211_width=1
c_probe_in212_width=1 | c_probe_in213_width=1 | c_probe_in214_width=1 | c_probe_in215_width=1
c_probe_in216_width=1 | c_probe_in217_width=1 | c_probe_in218_width=1 | c_probe_in219_width=1
c_probe_in21_width=1 | c_probe_in220_width=1 | c_probe_in221_width=1 | c_probe_in222_width=1
c_probe_in223_width=1 | c_probe_in224_width=1 | c_probe_in225_width=1 | c_probe_in226_width=1
c_probe_in227_width=1 | c_probe_in228_width=1 | c_probe_in229_width=1 | c_probe_in22_width=1
c_probe_in230_width=1 | c_probe_in231_width=1 | c_probe_in232_width=1 | c_probe_in233_width=1
c_probe_in234_width=1 | c_probe_in235_width=1 | c_probe_in236_width=1 | c_probe_in237_width=1
c_probe_in238_width=1 | c_probe_in239_width=1 | c_probe_in23_width=1 | c_probe_in240_width=1
c_probe_in241_width=1 | c_probe_in242_width=1 | c_probe_in243_width=1 | c_probe_in244_width=1
c_probe_in245_width=1 | c_probe_in246_width=1 | c_probe_in247_width=1 | c_probe_in248_width=1
c_probe_in249_width=1 | c_probe_in24_width=1 | c_probe_in250_width=1 | c_probe_in251_width=1
c_probe_in252_width=1 | c_probe_in253_width=1 | c_probe_in254_width=1 | c_probe_in255_width=1
c_probe_in25_width=1 | c_probe_in26_width=1 | c_probe_in27_width=1 | c_probe_in28_width=1
c_probe_in29_width=1 | c_probe_in2_width=1 | c_probe_in30_width=1 | c_probe_in31_width=1
c_probe_in32_width=1 | c_probe_in33_width=1 | c_probe_in34_width=1 | c_probe_in35_width=1
c_probe_in36_width=1 | c_probe_in37_width=1 | c_probe_in38_width=1 | c_probe_in39_width=1
c_probe_in3_width=1 | c_probe_in40_width=1 | c_probe_in41_width=1 | c_probe_in42_width=1
c_probe_in43_width=1 | c_probe_in44_width=1 | c_probe_in45_width=1 | c_probe_in46_width=1
c_probe_in47_width=1 | c_probe_in48_width=1 | c_probe_in49_width=1 | c_probe_in4_width=1
c_probe_in50_width=1 | c_probe_in51_width=1 | c_probe_in52_width=1 | c_probe_in53_width=1
c_probe_in54_width=1 | c_probe_in55_width=1 | c_probe_in56_width=1 | c_probe_in57_width=1
c_probe_in58_width=1 | c_probe_in59_width=1 | c_probe_in5_width=1 | c_probe_in60_width=1
c_probe_in61_width=1 | c_probe_in62_width=1 | c_probe_in63_width=1 | c_probe_in64_width=1
c_probe_in65_width=1 | c_probe_in66_width=1 | c_probe_in67_width=1 | c_probe_in68_width=1
c_probe_in69_width=1 | c_probe_in6_width=1 | c_probe_in70_width=1 | c_probe_in71_width=1
c_probe_in72_width=1 | c_probe_in73_width=1 | c_probe_in74_width=1 | c_probe_in75_width=1
c_probe_in76_width=1 | c_probe_in77_width=1 | c_probe_in78_width=1 | c_probe_in79_width=1
c_probe_in7_width=1 | c_probe_in80_width=1 | c_probe_in81_width=1 | c_probe_in82_width=1
c_probe_in83_width=1 | c_probe_in84_width=1 | c_probe_in85_width=1 | c_probe_in86_width=1
c_probe_in87_width=1 | c_probe_in88_width=1 | c_probe_in89_width=1 | c_probe_in8_width=1
c_probe_in90_width=1 | c_probe_in91_width=1 | c_probe_in92_width=1 | c_probe_in93_width=1
c_probe_in94_width=1 | c_probe_in95_width=1 | c_probe_in96_width=1 | c_probe_in97_width=1
c_probe_in98_width=1 | c_probe_in99_width=1 | c_probe_in9_width=1 | c_probe_out0_init_val=0x0
c_probe_out0_width=2 | c_probe_out100_init_val=0 | c_probe_out100_width=1 | c_probe_out101_init_val=0
c_probe_out101_width=1 | c_probe_out102_init_val=0 | c_probe_out102_width=1 | c_probe_out103_init_val=0
c_probe_out103_width=1 | c_probe_out104_init_val=0 | c_probe_out104_width=1 | c_probe_out105_init_val=0
c_probe_out105_width=1 | c_probe_out106_init_val=0 | c_probe_out106_width=1 | c_probe_out107_init_val=0
c_probe_out107_width=1 | c_probe_out108_init_val=0 | c_probe_out108_width=1 | c_probe_out109_init_val=0
c_probe_out109_width=1 | c_probe_out10_init_val=0 | c_probe_out10_width=1 | c_probe_out110_init_val=0
c_probe_out110_width=1 | c_probe_out111_init_val=0 | c_probe_out111_width=1 | c_probe_out112_init_val=0
c_probe_out112_width=1 | c_probe_out113_init_val=0 | c_probe_out113_width=1 | c_probe_out114_init_val=0
c_probe_out114_width=1 | c_probe_out115_init_val=0 | c_probe_out115_width=1 | c_probe_out116_init_val=0
c_probe_out116_width=1 | c_probe_out117_init_val=0 | c_probe_out117_width=1 | c_probe_out118_init_val=0
c_probe_out118_width=1 | c_probe_out119_init_val=0 | c_probe_out119_width=1 | c_probe_out11_init_val=0
c_probe_out11_width=1 | c_probe_out120_init_val=0 | c_probe_out120_width=1 | c_probe_out121_init_val=0
c_probe_out121_width=1 | c_probe_out122_init_val=0 | c_probe_out122_width=1 | c_probe_out123_init_val=0
c_probe_out123_width=1 | c_probe_out124_init_val=0 | c_probe_out124_width=1 | c_probe_out125_init_val=0
c_probe_out125_width=1 | c_probe_out126_init_val=0 | c_probe_out126_width=1 | c_probe_out127_init_val=0
c_probe_out127_width=1 | c_probe_out128_init_val=0 | c_probe_out128_width=1 | c_probe_out129_init_val=0
c_probe_out129_width=1 | c_probe_out12_init_val=0 | c_probe_out12_width=1 | c_probe_out130_init_val=0
c_probe_out130_width=1 | c_probe_out131_init_val=0 | c_probe_out131_width=1 | c_probe_out132_init_val=0
c_probe_out132_width=1 | c_probe_out133_init_val=0 | c_probe_out133_width=1 | c_probe_out134_init_val=0
c_probe_out134_width=1 | c_probe_out135_init_val=0 | c_probe_out135_width=1 | c_probe_out136_init_val=0
c_probe_out136_width=1 | c_probe_out137_init_val=0 | c_probe_out137_width=1 | c_probe_out138_init_val=0
c_probe_out138_width=1 | c_probe_out139_init_val=0 | c_probe_out139_width=1 | c_probe_out13_init_val=0
c_probe_out13_width=1 | c_probe_out140_init_val=0 | c_probe_out140_width=1 | c_probe_out141_init_val=0
c_probe_out141_width=1 | c_probe_out142_init_val=0 | c_probe_out142_width=1 | c_probe_out143_init_val=0
c_probe_out143_width=1 | c_probe_out144_init_val=0 | c_probe_out144_width=1 | c_probe_out145_init_val=0
c_probe_out145_width=1 | c_probe_out146_init_val=0 | c_probe_out146_width=1 | c_probe_out147_init_val=0
c_probe_out147_width=1 | c_probe_out148_init_val=0 | c_probe_out148_width=1 | c_probe_out149_init_val=0
c_probe_out149_width=1 | c_probe_out14_init_val=0 | c_probe_out14_width=1 | c_probe_out150_init_val=0
c_probe_out150_width=1 | c_probe_out151_init_val=0 | c_probe_out151_width=1 | c_probe_out152_init_val=0
c_probe_out152_width=1 | c_probe_out153_init_val=0 | c_probe_out153_width=1 | c_probe_out154_init_val=0
c_probe_out154_width=1 | c_probe_out155_init_val=0 | c_probe_out155_width=1 | c_probe_out156_init_val=0
c_probe_out156_width=1 | c_probe_out157_init_val=0 | c_probe_out157_width=1 | c_probe_out158_init_val=0
c_probe_out158_width=1 | c_probe_out159_init_val=0 | c_probe_out159_width=1 | c_probe_out15_init_val=0
c_probe_out15_width=1 | c_probe_out160_init_val=0 | c_probe_out160_width=1 | c_probe_out161_init_val=0
c_probe_out161_width=1 | c_probe_out162_init_val=0 | c_probe_out162_width=1 | c_probe_out163_init_val=0
c_probe_out163_width=1 | c_probe_out164_init_val=0 | c_probe_out164_width=1 | c_probe_out165_init_val=0
c_probe_out165_width=1 | c_probe_out166_init_val=0 | c_probe_out166_width=1 | c_probe_out167_init_val=0
c_probe_out167_width=1 | c_probe_out168_init_val=0 | c_probe_out168_width=1 | c_probe_out169_init_val=0
c_probe_out169_width=1 | c_probe_out16_init_val=0 | c_probe_out16_width=1 | c_probe_out170_init_val=0
c_probe_out170_width=1 | c_probe_out171_init_val=0 | c_probe_out171_width=1 | c_probe_out172_init_val=0
c_probe_out172_width=1 | c_probe_out173_init_val=0 | c_probe_out173_width=1 | c_probe_out174_init_val=0
c_probe_out174_width=1 | c_probe_out175_init_val=0 | c_probe_out175_width=1 | c_probe_out176_init_val=0
c_probe_out176_width=1 | c_probe_out177_init_val=0 | c_probe_out177_width=1 | c_probe_out178_init_val=0
c_probe_out178_width=1 | c_probe_out179_init_val=0 | c_probe_out179_width=1 | c_probe_out17_init_val=0
c_probe_out17_width=1 | c_probe_out180_init_val=0 | c_probe_out180_width=1 | c_probe_out181_init_val=0
c_probe_out181_width=1 | c_probe_out182_init_val=0 | c_probe_out182_width=1 | c_probe_out183_init_val=0
c_probe_out183_width=1 | c_probe_out184_init_val=0 | c_probe_out184_width=1 | c_probe_out185_init_val=0
c_probe_out185_width=1 | c_probe_out186_init_val=0 | c_probe_out186_width=1 | c_probe_out187_init_val=0
c_probe_out187_width=1 | c_probe_out188_init_val=0 | c_probe_out188_width=1 | c_probe_out189_init_val=0
c_probe_out189_width=1 | c_probe_out18_init_val=0 | c_probe_out18_width=1 | c_probe_out190_init_val=0
c_probe_out190_width=1 | c_probe_out191_init_val=0 | c_probe_out191_width=1 | c_probe_out192_init_val=0
c_probe_out192_width=1 | c_probe_out193_init_val=0 | c_probe_out193_width=1 | c_probe_out194_init_val=0
c_probe_out194_width=1 | c_probe_out195_init_val=0 | c_probe_out195_width=1 | c_probe_out196_init_val=0
c_probe_out196_width=1 | c_probe_out197_init_val=0 | c_probe_out197_width=1 | c_probe_out198_init_val=0
c_probe_out198_width=1 | c_probe_out199_init_val=0 | c_probe_out199_width=1 | c_probe_out19_init_val=0
c_probe_out19_width=1 | c_probe_out1_init_val=0 | c_probe_out1_width=1 | c_probe_out200_init_val=0
c_probe_out200_width=1 | c_probe_out201_init_val=0 | c_probe_out201_width=1 | c_probe_out202_init_val=0
c_probe_out202_width=1 | c_probe_out203_init_val=0 | c_probe_out203_width=1 | c_probe_out204_init_val=0
c_probe_out204_width=1 | c_probe_out205_init_val=0 | c_probe_out205_width=1 | c_probe_out206_init_val=0
c_probe_out206_width=1 | c_probe_out207_init_val=0 | c_probe_out207_width=1 | c_probe_out208_init_val=0
c_probe_out208_width=1 | c_probe_out209_init_val=0 | c_probe_out209_width=1 | c_probe_out20_init_val=0
c_probe_out20_width=1 | c_probe_out210_init_val=0 | c_probe_out210_width=1 | c_probe_out211_init_val=0
c_probe_out211_width=1 | c_probe_out212_init_val=0 | c_probe_out212_width=1 | c_probe_out213_init_val=0
c_probe_out213_width=1 | c_probe_out214_init_val=0 | c_probe_out214_width=1 | c_probe_out215_init_val=0
c_probe_out215_width=1 | c_probe_out216_init_val=0 | c_probe_out216_width=1 | c_probe_out217_init_val=0
c_probe_out217_width=1 | c_probe_out218_init_val=0 | c_probe_out218_width=1 | c_probe_out219_init_val=0
c_probe_out219_width=1 | c_probe_out21_init_val=0 | c_probe_out21_width=1 | c_probe_out220_init_val=0
c_probe_out220_width=1 | c_probe_out221_init_val=0 | c_probe_out221_width=1 | c_probe_out222_init_val=0
c_probe_out222_width=1 | c_probe_out223_init_val=0 | c_probe_out223_width=1 | c_probe_out224_init_val=0
c_probe_out224_width=1 | c_probe_out225_init_val=0 | c_probe_out225_width=1 | c_probe_out226_init_val=0
c_probe_out226_width=1 | c_probe_out227_init_val=0 | c_probe_out227_width=1 | c_probe_out228_init_val=0
c_probe_out228_width=1 | c_probe_out229_init_val=0 | c_probe_out229_width=1 | c_probe_out22_init_val=0
c_probe_out22_width=1 | c_probe_out230_init_val=0 | c_probe_out230_width=1 | c_probe_out231_init_val=0
c_probe_out231_width=1 | c_probe_out232_init_val=0 | c_probe_out232_width=1 | c_probe_out233_init_val=0
c_probe_out233_width=1 | c_probe_out234_init_val=0 | c_probe_out234_width=1 | c_probe_out235_init_val=0
c_probe_out235_width=1 | c_probe_out236_init_val=0 | c_probe_out236_width=1 | c_probe_out237_init_val=0
c_probe_out237_width=1 | c_probe_out238_init_val=0 | c_probe_out238_width=1 | c_probe_out239_init_val=0
c_probe_out239_width=1 | c_probe_out23_init_val=0 | c_probe_out23_width=1 | c_probe_out240_init_val=0
c_probe_out240_width=1 | c_probe_out241_init_val=0 | c_probe_out241_width=1 | c_probe_out242_init_val=0
c_probe_out242_width=1 | c_probe_out243_init_val=0 | c_probe_out243_width=1 | c_probe_out244_init_val=0
c_probe_out244_width=1 | c_probe_out245_init_val=0 | c_probe_out245_width=1 | c_probe_out246_init_val=0
c_probe_out246_width=1 | c_probe_out247_init_val=0 | c_probe_out247_width=1 | c_probe_out248_init_val=0
c_probe_out248_width=1 | c_probe_out249_init_val=0 | c_probe_out249_width=1 | c_probe_out24_init_val=0
c_probe_out24_width=1 | c_probe_out250_init_val=0 | c_probe_out250_width=1 | c_probe_out251_init_val=0
c_probe_out251_width=1 | c_probe_out252_init_val=0 | c_probe_out252_width=1 | c_probe_out253_init_val=0
c_probe_out253_width=1 | c_probe_out254_init_val=0 | c_probe_out254_width=1 | c_probe_out255_init_val=0
c_probe_out255_width=1 | c_probe_out25_init_val=0 | c_probe_out25_width=1 | c_probe_out26_init_val=0
c_probe_out26_width=1 | c_probe_out27_init_val=0 | c_probe_out27_width=1 | c_probe_out28_init_val=0
c_probe_out28_width=1 | c_probe_out29_init_val=0 | c_probe_out29_width=1 | c_probe_out2_init_val=0
c_probe_out2_width=1 | c_probe_out30_init_val=0 | c_probe_out30_width=1 | c_probe_out31_init_val=0
c_probe_out31_width=1 | c_probe_out32_init_val=0 | c_probe_out32_width=1 | c_probe_out33_init_val=0
c_probe_out33_width=1 | c_probe_out34_init_val=0 | c_probe_out34_width=1 | c_probe_out35_init_val=0
c_probe_out35_width=1 | c_probe_out36_init_val=0 | c_probe_out36_width=1 | c_probe_out37_init_val=0
c_probe_out37_width=1 | c_probe_out38_init_val=0 | c_probe_out38_width=1 | c_probe_out39_init_val=0
c_probe_out39_width=1 | c_probe_out3_init_val=0 | c_probe_out3_width=1 | c_probe_out40_init_val=0
c_probe_out40_width=1 | c_probe_out41_init_val=0 | c_probe_out41_width=1 | c_probe_out42_init_val=0
c_probe_out42_width=1 | c_probe_out43_init_val=0 | c_probe_out43_width=1 | c_probe_out44_init_val=0
c_probe_out44_width=1 | c_probe_out45_init_val=0 | c_probe_out45_width=1 | c_probe_out46_init_val=0
c_probe_out46_width=1 | c_probe_out47_init_val=0 | c_probe_out47_width=1 | c_probe_out48_init_val=0
c_probe_out48_width=1 | c_probe_out49_init_val=0 | c_probe_out49_width=1 | c_probe_out4_init_val=0
c_probe_out4_width=1 | c_probe_out50_init_val=0 | c_probe_out50_width=1 | c_probe_out51_init_val=0
c_probe_out51_width=1 | c_probe_out52_init_val=0 | c_probe_out52_width=1 | c_probe_out53_init_val=0
c_probe_out53_width=1 | c_probe_out54_init_val=0 | c_probe_out54_width=1 | c_probe_out55_init_val=0
c_probe_out55_width=1 | c_probe_out56_init_val=0 | c_probe_out56_width=1 | c_probe_out57_init_val=0
c_probe_out57_width=1 | c_probe_out58_init_val=0 | c_probe_out58_width=1 | c_probe_out59_init_val=0
c_probe_out59_width=1 | c_probe_out5_init_val=0 | c_probe_out5_width=1 | c_probe_out60_init_val=0
c_probe_out60_width=1 | c_probe_out61_init_val=0 | c_probe_out61_width=1 | c_probe_out62_init_val=0
c_probe_out62_width=1 | c_probe_out63_init_val=0 | c_probe_out63_width=1 | c_probe_out64_init_val=0
c_probe_out64_width=1 | c_probe_out65_init_val=0 | c_probe_out65_width=1 | c_probe_out66_init_val=0
c_probe_out66_width=1 | c_probe_out67_init_val=0 | c_probe_out67_width=1 | c_probe_out68_init_val=0
c_probe_out68_width=1 | c_probe_out69_init_val=0 | c_probe_out69_width=1 | c_probe_out6_init_val=0
c_probe_out6_width=1 | c_probe_out70_init_val=0 | c_probe_out70_width=1 | c_probe_out71_init_val=0
c_probe_out71_width=1 | c_probe_out72_init_val=0 | c_probe_out72_width=1 | c_probe_out73_init_val=0
c_probe_out73_width=1 | c_probe_out74_init_val=0 | c_probe_out74_width=1 | c_probe_out75_init_val=0
c_probe_out75_width=1 | c_probe_out76_init_val=0 | c_probe_out76_width=1 | c_probe_out77_init_val=0
c_probe_out77_width=1 | c_probe_out78_init_val=0 | c_probe_out78_width=1 | c_probe_out79_init_val=0
c_probe_out79_width=1 | c_probe_out7_init_val=0 | c_probe_out7_width=1 | c_probe_out80_init_val=0
c_probe_out80_width=1 | c_probe_out81_init_val=0 | c_probe_out81_width=1 | c_probe_out82_init_val=0
c_probe_out82_width=1 | c_probe_out83_init_val=0 | c_probe_out83_width=1 | c_probe_out84_init_val=0
c_probe_out84_width=1 | c_probe_out85_init_val=0 | c_probe_out85_width=1 | c_probe_out86_init_val=0
c_probe_out86_width=1 | c_probe_out87_init_val=0 | c_probe_out87_width=1 | c_probe_out88_init_val=0
c_probe_out88_width=1 | c_probe_out89_init_val=0 | c_probe_out89_width=1 | c_probe_out8_init_val=0
c_probe_out8_width=1 | c_probe_out90_init_val=0 | c_probe_out90_width=1 | c_probe_out91_init_val=0
c_probe_out91_width=1 | c_probe_out92_init_val=0 | c_probe_out92_width=1 | c_probe_out93_init_val=0
c_probe_out93_width=1 | c_probe_out94_init_val=0 | c_probe_out94_width=1 | c_probe_out95_init_val=0
c_probe_out95_width=1 | c_probe_out96_init_val=0 | c_probe_out96_width=1 | c_probe_out97_init_val=0
c_probe_out97_width=1 | c_probe_out98_init_val=0 | c_probe_out98_width=1 | c_probe_out99_init_val=0
c_probe_out99_width=1 | c_probe_out9_init_val=0 | c_probe_out9_width=1 | c_use_test_reg=1
c_xdevicefamily=artix7 | c_xlnx_hw_probe_info=DEFAULT | c_xsdb_slave_type=33 | core_container=NA
iptotal=1 | x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=vio
x_ipproduct=Vivado 2018.3 | x_ipvendor=xilinx.com | x_ipversion=3.0

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
cfgbvs-1=1 | rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
lutar-1=4 | pdrc-190=10 | timing-18=2

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | clocks=0.001880 | confidence_level_clock_activity=High
confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium | confidence_level_io_activity=High
confidence_level_overall=Medium | customer=TBD | customer_class=TBD | devstatic=0.071675
die=xc7a50tfgg484-2 | dsp_output_toggle=12.500000 | dynamic=0.002912 | effective_thetaja=2.8
enable_probability=0.990000 | family=artix7 | ff_toggle=12.500000 | flow_state=routed
heatsink=medium (Medium Profile) | i/o=0.000295 | input_toggle=12.500000 | junction_temp=25.2 (C)
logic=0.000355 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 | netlist_net_matched=NA | off-chip_power=0.000000 | on-chip_power=0.074587
output_enable=1.000000 | output_load=5.000000 | output_toggle=12.500000 | package=fgg484
pct_clock_constrained=1.000000 | pct_inputs_defined=100 | platform=nt64 | process=typical
ram_enable=50.000000 | ram_write=50.000000 | read_saif=False | set/reset_probability=0.000000
signal_rate=False | signals=0.000383 | simulation_file=None | speedgrade=-2
static_prob=False | temp_grade=commercial | thetajb=9.1 (C/W) | thetasa=4.6 (C/W)
toggle_rate=False | user_board_temp=25.0 (C) | user_effective_thetaja=2.8 | user_junc_temp=25.2 (C)
user_thetajb=9.1 (C/W) | user_thetasa=4.6 (C/W) | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000
vccadc_total_current=0.020000 | vccadc_voltage=1.800000 | vccaux_dynamic_current=0.000010 | vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000 | vccaux_static_current=0.012613
vccaux_total_current=0.012623 | vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000000 | vccbram_static_current=0.000161
vccbram_total_current=0.000161 | vccbram_voltage=1.000000 | vccint_dynamic_current=0.002649 | vccint_static_current=0.009511
vccint_total_current=0.012160 | vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000
vcco12_total_current=0.000000 | vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000
vcco135_total_current=0.000000 | vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000
vcco15_total_current=0.000000 | vcco15_voltage=1.500000 | vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000
vcco18_total_current=0.000000 | vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000
vcco25_total_current=0.000000 | vcco25_voltage=2.500000 | vcco33_dynamic_current=0.000074 | vcco33_static_current=0.001000
vcco33_total_current=0.001074 | vcco33_voltage=3.300000 | version=2018.3

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=2 | bufgctrl_util_percentage=6.25
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=20 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=10 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=20 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=5 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=120 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=75 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=150 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=75 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
bscane2_functional_category=Others | bscane2_used=1 | bufg_functional_category=Clock | bufg_used=2
carry4_functional_category=CarryLogic | carry4_used=12 | fdce_functional_category=Flop & Latch | fdce_used=171
fdpe_functional_category=Flop & Latch | fdpe_used=40 | fdre_functional_category=Flop & Latch | fdre_used=759
fdse_functional_category=Flop & Latch | fdse_used=10 | ibuf_functional_category=IO | ibuf_used=1
lut1_functional_category=LUT | lut1_used=22 | lut2_functional_category=LUT | lut2_used=98
lut3_functional_category=LUT | lut3_used=131 | lut4_functional_category=LUT | lut4_used=132
lut5_functional_category=LUT | lut5_used=105 | lut6_functional_category=LUT | lut6_used=143
obuf_functional_category=IO | obuf_used=2 | ramd32_functional_category=Distributed Memory | ramd32_used=36
rams32_functional_category=Distributed Memory | rams32_used=12
slice_logic
f7_muxes_available=16300 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=8150 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=24 | lut_as_logic_available=32600 | lut_as_logic_fixed=0
lut_as_logic_used=553 | lut_as_logic_util_percentage=1.70 | lut_as_memory_available=9600 | lut_as_memory_fixed=0
lut_as_memory_used=24 | lut_as_memory_util_percentage=0.25 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
register_as_flip_flop_available=65200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=980 | register_as_flip_flop_util_percentage=1.50
register_as_latch_available=65200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=32600 | slice_luts_fixed=0 | slice_luts_used=577 | slice_luts_util_percentage=1.77
slice_registers_available=65200 | slice_registers_fixed=0 | slice_registers_used=980 | slice_registers_util_percentage=1.50
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=24 | lut_as_logic_available=32600 | lut_as_logic_fixed=0
lut_as_logic_used=553 | lut_as_logic_util_percentage=1.70 | lut_as_memory_available=9600 | lut_as_memory_fixed=0
lut_as_memory_used=24 | lut_as_memory_util_percentage=0.25 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 | lut_in_front_of_the_register_is_unused_used=405 | lut_in_front_of_the_register_is_used_fixed=405 | lut_in_front_of_the_register_is_used_used=95
register_driven_from_outside_the_slice_fixed=95 | register_driven_from_outside_the_slice_used=500 | register_driven_from_within_the_slice_fixed=500 | register_driven_from_within_the_slice_used=480
slice_available=8150 | slice_fixed=0 | slice_registers_available=65200 | slice_registers_fixed=0
slice_registers_used=980 | slice_registers_util_percentage=1.50 | slice_used=260 | slice_util_percentage=3.19
slicel_fixed=0 | slicel_used=156 | slicem_fixed=0 | slicem_used=104
unique_control_sets_available=8150 | unique_control_sets_fixed=8150 | unique_control_sets_used=78 | unique_control_sets_util_percentage=0.96
using_o5_and_o6_fixed=0.96 | using_o5_and_o6_used=24 | using_o5_output_only_fixed=24 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=0
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=1 | bscane2_util_percentage=25.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a50tfgg484-2
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=VIO_TEST | -verilog_define=default::[not_specified]
usage
elapsed=00:00:11s | hls_ip=0 | memory_gain=483.863MB | memory_peak=767.773MB