`timescale 1ns / 1ps
module count_tb(

    );
    
reg    clk_i;
reg    rst_n_i;

  initial begin    
      clk_i = 0;
      rst_n_i = 0;
      #200;
      rst_n_i = 'b1;
  end

 always #5 clk_i = ~clk_i;

count_module u_test(  
    .clk(clk_i),   
    .rst_n(rst_n_i)
);



endmodule
