# compile verilog/system verilog design source files
verilog xil_defaultlib  \
"../../../../SIMULATION_TEST.srcs/sources_1/new/count_module.v" \
"../../../../SIMULATION_TEST.srcs/sim_1/new/count_tb.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
