/////////////////////
//www.hellofpga.com//
/////////////////////
`timescale 1ns / 1ps
module KEY_TEST(
    input CLK,
    input RSTn,
    output LED1,
    output LED2,
    input KEY1,
    input KEY2
);

reg LED1_r=0;
reg LED2_r=0;

always@(posedge CLK or negedge RSTn)begin
    if(!RSTn)begin
        LED1_r <= 0;
        LED2_r <= 0;
    end
    else begin
        if(KEY1==0) LED1_r <= 1'b1;
        else LED1_r <= 1'b0;
       
        if(KEY2==0) LED2_r <= 1'b1;
        else LED2_r <= 1'b0;
    end
end

assign LED1 = LED1_r;
assign LED2 = LED2_r;

endmodule
