### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2405991
date_generated | Fri Nov 14 16:33:31 2025 | os_platform | WIN64
product_version | Vivado v2018.3 (64-bit) | project_id | 823476529e7648b79254f3ea0e3a9f09
project_iteration | 5 | random_id | b8c6a05b9ec65faeb2d33a3e52056931
registration_id | b8c6a05b9ec65faeb2d33a3e52056931 | route_design | TRUE
target_device | xc7a50t | target_family | artix7
target_package | fgg484 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | AMD Ryzen 9 7945HX with Radeon Graphics | cpu_speed | 2495 MHz
os_name | Microsoft Windows 8 or later , 64-bit | os_release | major release (build 9200)
system_ram | 67.000 GB | total_processors | 1

vivado_usage

gui_handlers
basedialog_apply=3 | basedialog_cancel=7 | basedialog_no=1 | basedialog_ok=16
basedialog_yes=3 | createconstraintsfilepanel_file_name=1 | createsrcfiledialog_file_name=1 | filesetpanel_file_set_panel_tree=33
flownavigatortreepanel_flow_navigator_tree=42 | fpgachooser_fpga_table=4 | gettingstartedview_create_new_project=1 | mainmenumgr_file=8
mainmenumgr_project=3 | maintoolbarmgr_run=5 | netlistschematicview_show_io_ports_in_this_schematic=2 | pacommandnames_auto_connect_target=7
pacommandnames_goto_netlist_design=1 | pacommandnames_open_project=2 | pacommandnames_run_synthesis=4 | pacommandnames_save_design=1
paviews_project_summary=5 | programfpgadialog_program=5 | projectnamechooser_choose_project_location=1 | projectnamechooser_project_name=1
projecttab_reload=1 | saveprojectutils_cancel=2 | saveprojectutils_save=9 | settingsprojectgeneralpage_choose_device_for_your_project=3
signaltablepanel_signal_table=10 | srcchooserpanel_create_file=1

java_command_handlers
addsources=1 | autoconnecttarget=7 | launchprogramfpga=5 | newproject=1
openhardwaremanager=12 | openproject=2 | openrecenttarget=7 | programdevice=5
runbitgen=9 | runschematic=1 | runsynthesis=4 | savedesign=1
showview=1 | toolssettings=5

other_data
guimode=11

project_data
constraintsetcount=1 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=1 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=1 | totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 | fdce=2 | ibuf=4 | lut1=3
obuf=2 | vcc=1
pre_unisim_transformation
bufg=1 | fdce=2 | ibuf=4 | lut1=3
obuf=2 | vcc=1

report_drc
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]
results
timing-18=5

report_power
command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]
usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | clocks=0.000210 | confidence_level_clock_activity=High
confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium | confidence_level_io_activity=Medium
confidence_level_overall=Medium | customer=TBD | customer_class=TBD | devstatic=0.071673
die=xc7a50tfgg484-2 | dsp_output_toggle=12.500000 | dynamic=0.000993 | effective_thetaja=2.8
enable_probability=0.990000 | family=artix7 | ff_toggle=12.500000 | flow_state=routed
heatsink=medium (Medium Profile) | i/o=0.000765 | input_toggle=12.500000 | junction_temp=25.2 (C)
logic=0.000001 | mgtavcc_dynamic_current=0.000000 | mgtavcc_static_current=0.000000 | mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 | mgtavtt_dynamic_current=0.000000 | mgtavtt_static_current=0.000000 | mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 | netlist_net_matched=NA | off-chip_power=0.000000 | on-chip_power=0.072666
output_enable=1.000000 | output_load=5.000000 | output_toggle=12.500000 | package=fgg484
pct_clock_constrained=0.000000 | pct_inputs_defined=25 | platform=nt64 | process=typical
ram_enable=50.000000 | ram_write=50.000000 | read_saif=False | set/reset_probability=0.000000
signal_rate=False | signals=0.000017 | simulation_file=None | speedgrade=-2
static_prob=False | temp_grade=commercial | thetajb=9.1 (C/W) | thetasa=4.6 (C/W)
toggle_rate=False | user_board_temp=25.0 (C) | user_effective_thetaja=2.8 | user_junc_temp=25.2 (C)
user_thetajb=9.1 (C/W) | user_thetasa=4.6 (C/W) | vccadc_dynamic_current=0.000000 | vccadc_static_current=0.020000
vccadc_total_current=0.020000 | vccadc_voltage=1.800000 | vccaux_dynamic_current=0.000027 | vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 | vccaux_io_total_current=0.000000 | vccaux_io_voltage=1.800000 | vccaux_static_current=0.012613
vccaux_total_current=0.012640 | vccaux_voltage=1.800000 | vccbram_dynamic_current=0.000000 | vccbram_static_current=0.000161
vccbram_total_current=0.000161 | vccbram_voltage=1.000000 | vccint_dynamic_current=0.000264 | vccint_static_current=0.009509
vccint_total_current=0.009773 | vccint_voltage=1.000000 | vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000
vcco12_total_current=0.000000 | vcco12_voltage=1.200000 | vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000
vcco135_total_current=0.000000 | vcco135_voltage=1.350000 | vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000
vcco15_total_current=0.000000 | vcco15_voltage=1.500000 | vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000
vcco18_total_current=0.000000 | vcco18_voltage=1.800000 | vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000
vcco25_total_current=0.000000 | vcco25_voltage=2.500000 | vcco33_dynamic_current=0.000206 | vcco33_static_current=0.001000
vcco33_total_current=0.001206 | vcco33_voltage=3.300000 | version=2018.3

report_utilization
clocking
bufgctrl_available=32 | bufgctrl_fixed=0 | bufgctrl_used=1 | bufgctrl_util_percentage=3.13
bufhce_available=72 | bufhce_fixed=0 | bufhce_used=0 | bufhce_util_percentage=0.00
bufio_available=20 | bufio_fixed=0 | bufio_used=0 | bufio_util_percentage=0.00
bufmrce_available=10 | bufmrce_fixed=0 | bufmrce_used=0 | bufmrce_util_percentage=0.00
bufr_available=20 | bufr_fixed=0 | bufr_used=0 | bufr_util_percentage=0.00
mmcme2_adv_available=5 | mmcme2_adv_fixed=0 | mmcme2_adv_used=0 | mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 | plle2_adv_fixed=0 | plle2_adv_used=0 | plle2_adv_util_percentage=0.00
dsp
dsps_available=120 | dsps_fixed=0 | dsps_used=0 | dsps_util_percentage=0.00
io_standard
blvds_25=0 | diff_hstl_i=0 | diff_hstl_i_18=0 | diff_hstl_ii=0
diff_hstl_ii_18=0 | diff_hsul_12=0 | diff_mobile_ddr=0 | diff_sstl135=0
diff_sstl135_r=0 | diff_sstl15=0 | diff_sstl15_r=0 | diff_sstl18_i=0
diff_sstl18_ii=0 | hstl_i=0 | hstl_i_18=0 | hstl_ii=0
hstl_ii_18=0 | hsul_12=0 | lvcmos12=0 | lvcmos15=0
lvcmos18=0 | lvcmos25=0 | lvcmos33=1 | lvds_25=0
lvttl=0 | mini_lvds_25=0 | mobile_ddr=0 | pci33_3=0
ppds_25=0 | rsds_25=0 | sstl135=0 | sstl135_r=0
sstl15=0 | sstl15_r=0 | sstl18_i=0 | sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=75 | block_ram_tile_fixed=0 | block_ram_tile_used=0 | block_ram_tile_util_percentage=0.00
ramb18_available=150 | ramb18_fixed=0 | ramb18_used=0 | ramb18_util_percentage=0.00
ramb36_fifo_available=75 | ramb36_fifo_fixed=0 | ramb36_fifo_used=0 | ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock | bufg_used=1 | fdce_functional_category=Flop & Latch | fdce_used=2
ibuf_functional_category=IO | ibuf_used=4 | lut1_functional_category=LUT | lut1_used=3
obuf_functional_category=IO | obuf_used=2
slice_logic
f7_muxes_available=16300 | f7_muxes_fixed=0 | f7_muxes_used=0 | f7_muxes_util_percentage=0.00
f8_muxes_available=8150 | f8_muxes_fixed=0 | f8_muxes_used=0 | f8_muxes_util_percentage=0.00
lut_as_logic_available=32600 | lut_as_logic_fixed=0 | lut_as_logic_used=3 | lut_as_logic_util_percentage=<0.01
lut_as_memory_available=9600 | lut_as_memory_fixed=0 | lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=65200 | register_as_flip_flop_fixed=0 | register_as_flip_flop_used=2 | register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=65200 | register_as_latch_fixed=0 | register_as_latch_used=0 | register_as_latch_util_percentage=0.00
slice_luts_available=32600 | slice_luts_fixed=0 | slice_luts_used=3 | slice_luts_util_percentage=<0.01
slice_registers_available=65200 | slice_registers_fixed=0 | slice_registers_used=2 | slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0 | lut_as_distributed_ram_used=0 | lut_as_logic_available=32600 | lut_as_logic_fixed=0
lut_as_logic_used=3 | lut_as_logic_util_percentage=<0.01 | lut_as_memory_available=9600 | lut_as_memory_fixed=0
lut_as_memory_used=0 | lut_as_memory_util_percentage=0.00 | lut_as_shift_register_fixed=0 | lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 | register_driven_from_outside_the_slice_used=0 | register_driven_from_within_the_slice_fixed=0 | register_driven_from_within_the_slice_used=2
slice_available=8150 | slice_fixed=0 | slice_registers_available=65200 | slice_registers_fixed=0
slice_registers_used=2 | slice_registers_util_percentage=<0.01 | slice_used=1 | slice_util_percentage=0.01
slicel_fixed=0 | slicel_used=1 | slicem_fixed=0 | slicem_used=0
unique_control_sets_available=8150 | unique_control_sets_fixed=8150 | unique_control_sets_used=1 | unique_control_sets_util_percentage=0.01
using_o5_and_o6_fixed=0.01 | using_o5_and_o6_used=0 | using_o5_output_only_fixed=0 | using_o5_output_only_used=0
using_o6_output_only_fixed=0 | using_o6_output_only_used=3
specific_feature
bscane2_available=4 | bscane2_fixed=0 | bscane2_used=0 | bscane2_util_percentage=0.00
capturee2_available=1 | capturee2_fixed=0 | capturee2_used=0 | capturee2_util_percentage=0.00
dna_port_available=1 | dna_port_fixed=0 | dna_port_used=0 | dna_port_util_percentage=0.00
efuse_usr_available=1 | efuse_usr_fixed=0 | efuse_usr_used=0 | efuse_usr_util_percentage=0.00
frame_ecce2_available=1 | frame_ecce2_fixed=0 | frame_ecce2_used=0 | frame_ecce2_util_percentage=0.00
icape2_available=2 | icape2_fixed=0 | icape2_used=0 | icape2_util_percentage=0.00
pcie_2_1_available=1 | pcie_2_1_fixed=0 | pcie_2_1_used=0 | pcie_2_1_util_percentage=0.00
startupe2_available=1 | startupe2_fixed=0 | startupe2_used=0 | startupe2_util_percentage=0.00
xadc_available=1 | xadc_fixed=0 | xadc_used=0 | xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xc7a50tfgg484-2
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=KEY_TEST | -verilog_define=default::[not_specified]
usage
elapsed=00:00:11s | hls_ip=0 | memory_gain=461.816MB | memory_peak=734.398MB