{"id":6145,"date":"2024-03-02T14:00:52","date_gmt":"2024-03-02T06:00:52","guid":{"rendered":"http:\/\/www.hellofpga.com\/?p=6145"},"modified":"2024-10-27T22:58:02","modified_gmt":"2024-10-27T14:58:02","slug":"pulse-width-modulation-audio","status":"publish","type":"post","link":"http:\/\/www.hellofpga.com\/index.php\/2024\/03\/02\/pulse-width-modulation-audio\/","title":{"rendered":"Xillinux \u7ae0\u8282\u5341\u4e94 \u5c06\u666e\u901a\u8033\u673a\u8fde\u63a5\u5230 digital output pin \u5e76\u64ad\u653e\u97f3\u4e50 \uff08\u9002\u7528\u4e8eSmart Zynq SP\/SP2\/SL\uff09"},"content":{"rendered":"\n<p>\u672c\u6587\u6839\u636e Xillinux \uff08xillybus\uff09\u5b98\u65b9\u7684\u5b50\u7f51\u7ad9 www.01signal.com \u4e2d\u7684\u5185\u5bb9\u8f6c\u8f7d\u6574\u7406\u800c\u6765\uff0c\u5982\u5bf9\u539f\u59cb\u5185\u5bb9\u611f\u5174\u8da3\u7684\u53ef\u8bbf\u95ee\u4e0b\u5217\u94fe\u63a5\u8fdb\u884c\u67e5\u770b&nbsp;<a href=\"https:\/\/www.01signal.com\/zh\/xillinux\/linux-gui-desktop-on-microsoft-windows\/\">01signal:<\/a><a href=\"https:\/\/www.01signal.com\/zh\/xillinux\/pulse-width-modulation-audio\/\" target=\"_blank\" rel=\"noreferrer noopener\">\u5c06\u666e\u901a\u8033\u673a\u8fde\u63a5\u5230 digital output pin \u5e76\u542c\u97f3\u4e50<\/a><\/p>\n\n\n\n<p>\u4e5f\u611f\u8c22xillybus \u5b98\u65b9\u5bf9\u539f\u59cb\u5185\u5bb9\u7684\u68b3\u7406\uff0c \u672c\u6587\u4ec5\u5728\u4e0a\u8ff0\u5185\u5bb9\u4e2d\u5bf9\u6587\u4e2d\u90e8\u5206\u7ffb\u8bd1\u5185\u5bb9\u505a\u4e86\u7b80\u5355\u5fae\u8c03\uff0c\u4ee5\u4fbf\u66f4\u597d\u7684\u7406\u89e3\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u4ecb\u7ecd<\/strong><\/h2>\n\n\n\n<p>\u672c\u6559\u7a0b\u4ecb\u7ecd\u5982\u4f55\u5c06\u666e\u901a\u8033\u673a\u8fde\u63a5\u5230 Smart Zynq \u677f\u5e76\u542c\u97f3\u4e50\u3002\u8be5\u9879\u76ee\u7684\u76ee\u7684\u662f\u6f14\u793a\u5982\u4f55\u4f7f\u7528 Xillybus stream \u5411 FPGA\u53d1\u9001\u8fde\u7eed\u6570\u636e\u3002\u6b64\u5904\u8fd8\u5c55\u793a\u4e86\u5b9e\u73b0 PWM \u8c03\u8bd5\u7684 Verilog \u4ee3\u7801\u3002<\/p>\n\n\n\n<p>Smart Zynq \u672c\u8eab\u4e0d\u5e26\u97f3\u9891\u8f93\u51fa\u7535\u8def\uff0c\u4e0d\u5177\u6709\u97f3\u9891\u7684\u8f93\u51fa\u80fd\u529b\u3002\u672c\u6587\u91c7\u7528\u7528PWM\u7f16\u7801\u7684\u65b9\u5f0f\u6765\u8ba9digital output pin\uff08\u6570\u5b57GPIO\u53e3\uff09\u5b9e\u73b0\u6a21\u62df\u97f3\u9891\u7684\u8f93\u51fa\u529f\u80fd\u3002\uff08\u901a\u5e38\u97f3\u9891\u7684\u8f93\u51fa\u4f1a\u4f7f\u7528\u4e00\u79cd\u66f4\u4e3a\u590d\u6742\u7684\u6280\u672f\uff08<strong>Sigma-Delata<\/strong>\uff09\u3002\u8be5\u6280\u672f\u53ef\u4ee5\u5728 FPGA\u4e0a\u5b9e\u73b0\uff0c\u4f46\u7406\u8bba\u80cc\u666f\u66f4\u96be\u7406\u89e3\uff0c\u672c\u6587\u4e2d\u6240\u91c7\u7528\u7684\u7528PWM\u6765\u6a21\u62df\u8f93\u51fa\u97f3\u9891\u7684\u65b9\u5f0f\u76f8\u8f83\u800c\u8a00\u4f1a\u66f4\u5bb9\u6613\u5b9e\u73b0\u4e00\u4e9b\uff09\u3002<\/p>\n\n\n\n<p>\u7528\u6b64\u65b9\u6cd5\u5b9e\u73b0\u97f3\u9891\u8f93\u51fa\u7684\u53e6\u4e00\u4e2a\u7f3a\u70b9\u662f\u5b83\u7684 sample rate\uff08\u91c7\u6837\u7387\uff09 \u4e0d\u51c6\u786e\uff0848828 Hz \u800c\u4e0d\u662f 48000 Hz\uff09\u3002\u901a\u8fc7\u66f4\u6539 logic\u4f7f\u7528\u7684 clock \u7684\u9891\u7387\u53ef\u4ee5\u8f7b\u677e\u89e3\u51b3\u6b64\u95ee\u9898\u3002\u6b64\u5904\u672a\u663e\u793a\u4e3a\u6b64\u76ee\u7684\u64cd\u4f5c clocks \u7684\u4e3b\u9898\uff0c\u56e0\u4e3a\u6b64\u793a\u4f8b\u4fa7\u91cd\u4e8e\u7b80\u5355\u6027\u800c\u4e0d\u662f\u51c6\u786e\u6027\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u672c\u6b21\u6f14\u793a\u7684\u8bbe\u5907\u662f\uff1a<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Smart Zynq \u677f\uff08SP\uff0cSP2  \u6216 SL\uff09\u3002<\/li>\n\n\n\n<li>\u4e00\u526f\u666e\u901a\u7684\u6a21\u62df\u8033\u673a<strong>\uff08\u9898\u5916\u8bdd\uff1a\u56e0\u4e3a\u8be5\u6a21\u62df\u97f3\u9891\u8f93\u51fa\u7684\u65b9\u5f0f\u5bf9\u8033\u673a\u6709\u53ef\u80fd\u9020\u6210\u635f\u574f\uff0c\u6240\u4ee5\u8bf7\u4e0d\u8981\u62ff\u5f88\u8d35\u7684\u8033\u673a\u6765\u505a\u6d4b\u8bd5\uff0c\u6211\u77e5\u9053\u6709\u4e9b\u7a0b\u5e8f\u5458\u7684\u8033\u673a\u5e76\u4e0d\u4fbf\u5b9c\uff09<\/strong>\u3002<\/li>\n\n\n\n<li>\u9cc4\u9c7c\u5939\u548c\u7535\u7ebf\uff0c\u6216\u8005\u5176\u4ed6\u53ef\u4ee5\u8fde\u63a5PIN\u811a\u7684\u65b9\u5f0f\u3002<\/li>\n\n\n\n<li>\u53ef\u9009\u7684\uff1a \u4e00\u4e2a 50\u03a9-200\u03a9\u7535\u963b\u3002 \u6dfb\u52a0\u8fd9\u4e2a\u7535\u963b\u7684\u76ee\u7684\u662f\u4e3a\u4e86\u4fdd\u62a4\u8033\u673a\u548c Smart Zynq \u4e3b\u677f\u514d\u53d7\u8fc7\u5927\u7535\u6d41\u7684\u5f71\u54cd\u3002\u8be5\u793a\u4f8b\u5728\u6ca1\u6709\u8fd9\u4e2a\u7535\u963b\u7684\u60c5\u51b5\u4e0b\u4e5f\u53ef\u4ee5\u5de5\u4f5c\uff0c\u4f46\u4f1a\u5b58\u5728\u635f\u574f\u7535\u5b50\u8bbe\u5907\u7684\u98ce\u9669\u3002<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u51c6\u5907 Vivado \u9879\u76ee<\/strong><\/h2>\n\n\n\n<p>\u4ece demo bundle\u7684 zip \u6587\u4ef6\uff08 boot partition kit\uff09\u521b\u5efa\u4e00\u4e2a\u65b0\u7684 Vivado \u9879\u76ee\u3002\u5728\u6587\u672c\u7f16\u8f91\u5668\u4e2d\u6253\u5f00 verilog\/src\/xillydemo.v \u3002\u5220\u9664\u6807\u8bb0\u4e3a\u201cPART 2\u201d\u7684\u4ee3\u7801\u90e8\u5206\u3002\u76f8\u53cd\uff0c\u63d2\u5165\u4ee5\u4e0b\u4ee3\u7801\u7247\u6bb5\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">\/*\n    * PART 2\n    * ======\n    *\n    * This code demonstrates a PWM-based audio output\n    *\/\n\n   reg [10:0]   pwm_level, threshold_left, threshold_right;\n   reg \t\tpwm_left, pwm_right;\n   reg \t\tfifo_out_valid;\n   wire [31:0] \tfifo_out;\n   wire \tfifo_empty;\n\n   wire \tfifo_rd_en = !fifo_out_valid &amp;&amp; !fifo_empty;\n   wire \tnext_word = (pwm_level == 11'h7ff);\n\n   assign J6 = { pwm_right, pwm_left };\n\n   always @(posedge bus_clk)\n     begin\n\tpwm_level &lt;= pwm_level + 1;\n\n\tif (next_word &amp;&amp; fifo_out_valid)\n\t  begin\n\t     \/\/ The audio samples are signed integers. Change them to\n\t     \/\/ unsigned by adding 1024.\n\t     threshold_left &lt;= fifo_out[15:5] + 1024;\n\t     threshold_right &lt;= fifo_out[31:21] + 1024;\n\t  end\n\telse if (next_word) \/\/ FIFO's output not valid, keep silent\n\t  begin\n\t     threshold_left &lt;= 0;\n\t     threshold_right &lt;= 0;\n\t  end\n\n\tpwm_left &lt;= (threshold_left &gt; pwm_level);\n\tpwm_right &lt;= (threshold_right &gt; pwm_level);\n\n\tif (fifo_rd_en)\n\t  fifo_out_valid &lt;= 1;\n\telse if (next_word)\n\t  fifo_out_valid &lt;= 0;\n     end\n\n   \/\/ 32-bit FIFO for audio samples\n   fifo_32x512 fifo_32\n     (\n      .clk(bus_clk),\n      \/\/ Interface with Xillybus IP core\n      .srst(!user_w_write_32_open),\n      .din(user_w_write_32_data),\n      .wr_en(user_w_write_32_wren),\n      .full(user_w_write_32_full),\n\n      \/\/ Interface with application logic\n      .rd_en(fifo_rd_en),\n      .dout(fifo_out),\n      .empty(fifo_empty)\n      );\n\n   \/\/ Send the text \"PWM\" to reassure that the correct bitstream is used.\n   assign user_r_read_32_eof = 0;\n   assign user_r_read_32_empty = 0;\n   assign user_r_read_32_data = 32'h0a_4d_57_50; \/\/ \"PWM\" + LF<\/pre>\n\n\n\n<p>\u6216\u8005\uff0c\u4ece<a href=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/xillydemo.v\" target=\"_blank\" rel=\"noreferrer noopener\"><strong>\u6b64\u5904<\/strong><\/a>\u4e0b\u8f7d\u4fee\u6539\u540e\u7684 xillydemo.v \u6587\u4ef6\u3002<\/p>\n\n\n\n<p>\u6309\u7167\u4e0e\u4e3a demo bundle\u521b\u5efa bitstream \u6587\u4ef6\u76f8\u540c\u7684\u65b9\u6cd5\u4ece\u521a\u624d\u66f4\u6539\u540e\u7684\u9879\u76ee\u521b\u5efa bitstream \u6587\u4ef6\u3002\u540c\u6837\u4ee5\u76f8\u540c\u7684\u65b9\u5f0f\u5c06 bitstream \u6587\u4ef6\u590d\u5236\u5230 TF \u5361\uff08\u7528\u6b64\u9879\u76ee\u521b\u5efa\u7684\u6587\u4ef6\u8986\u76d6\u65e7\u7684 xillydemo.bit \u6587\u4ef6\uff09\u3002<strong>( \u521b\u5efabitstream\u7684\u65b9\u6cd5\uff0c\u4ee5\u53ca\u590d\u5236bitstream\u90e8\u5206\u7684\u64cd\u4f5c\u8bf7\u53c2\u8003  <a href=\"http:\/\/www.hellofpga.com\/index.php\/2023\/10\/17\/xillinux-demo-bundle\/\">Xillinux \u7ae0\u8282\u4e8c TF\u5361\u51c6\u5907\u5de5\u4f5c\u4e4b demo bundle \u7684\u4f7f\u7528\u8bf4\u660e<\/a>&nbsp;)<\/strong><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u8fde\u63a5\u8033\u673a<\/strong><\/h2>\n\n\n\n<p>\u8033\u673a\u7684\u8fde\u63a5\u6211\u4eec\u9700\u8981\u8fde\u63a5\u4e09\u6839\u4fe1\u53f7\u7ebf\uff0c\u5373\u5de6\u8033\u97f3\u9891\u4fe1\u53f7\uff0c\u53f3\u8033\u97f3\u9891\u4fe1\u53f7\uff0c\u4ee5\u53caGND<\/p>\n\n\n\n<p>\u5c06 50\u03a9-200\u03a9 \u7684\u7535\u963b\u8fde\u63a5\u5230\u627f\u8f7d\u97f3\u9891\u4fe1\u53f7\u7684 I\/O \u7ba1\u811aPIN\u4e0a \uff1a J6\/1 \uff08\u5de6\u8033\uff09\u6216 J6\/2 \uff08\u53f3\u8033\uff09\u3002\u4e3a\u4e86\u627e\u5230 J6\uff0c\u8bf7\u5728 Smart Zynq \u677f\u80cc\u9762\u67e5\u627e\u5199\u6709\u201cBank 33 VCCIO Vadj\u201d\u7684\u4f4d\u7f6e\u3002\u9760\u8fd1\u6b64\u6807\u8bb0\u7684 \u6392\u9488\u884c\u662f\u6211\u4eec\u5c06\u4f7f\u7528\u7684\u5f15\u811a\u63a5\u53e3 \u3002\u56e0\u6b64\uff0c J6\/1 \u662f\u6700\u63a5\u8fd1 HDMI \u8fde\u63a5\u5668\u7684\u5f15\u811a \u3002(\u8be6\u7ec6\u4f4d\u7f6e\u53ef\u53c2\u8003\u4e0b\u56fe)<\/p>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"499\" height=\"387\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/1709340844542.png\" alt=\"\" class=\"wp-image-6289\" style=\"width:272px;height:auto\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/1709340844542.png 499w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/1709340844542-300x233.png 300w\" sizes=\"auto, (max-width: 499px) 100vw, 499px\" \/><\/figure>\n\n\n\n<p>\u5c06\u7535\u963b\u7684\u53e6\u4e00\u7aef\u8fde\u63a5\u5230\u8033\u673a\u63d2\u5934\u7684\u5c16\u7aef\u3002\u4e5f\u53ef\u4ee5\u7528\u9cc4\u9c7c\u5939\u6765\u8fdb\u884c\u8fde\u63a5\u3002<strong>(\u5907\u6ce8\uff0c\u5982\u679c\u60a8\u7684\u8033\u673a\u662f\u56db\u6bb5\u5f0f\u7684\u8033\u673a\u63a5\u53e3\uff0cGND\u548cMIC\u7684\u4f4d\u7f6e\u6709\u4e24\u79cd\u6807\u51c6\uff0c\u4e92\u76f8\u76f8\u53cd\uff0c\u8bf7\u81ea\u884c\u5c1d\u8bd5)<\/strong><\/p>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"586\" height=\"231\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image.png\" alt=\"\" class=\"wp-image-6293\" style=\"width:337px;height:auto\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image.png 586w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-300x118.png 300w\" sizes=\"auto, (max-width: 586px) 100vw, 586px\" \/><\/figure>\n\n\n\n<p>\u5c06\u8033\u673a\u63d2\u5934\u7684\u5957\u7b52\u90e8\u5206\u8fde\u63a5\u5230 Smart Zynq\u7684 GND\u4e0a\u3002 \u6392\u9488\u7684GND\u5b9a\u4f4d\u5728 J6\/35 \u6216 J6\/36\u3002\u4f46\u4e0d\u5efa\u8bae\u4f7f\u7528\u8fd9\u4e9b pins\uff0c\u56e0\u4e3a\u5b83\u4eec\u592a\u63a5\u8fd1\u7535\u6e90\u7ba1\u811a<strong>\uff08\u5982\u4f7f\u7528\u9cc4\u9c7c\u5939\u6709\u78b0\u89e6\u5230\u7535\u6e90\u548c\u5730\u9020\u6210\u77ed\u8def\u6709\u786c\u4ef6\u635f\u574f\u7684\u98ce\u9669\uff09<\/strong>\u3002<\/p>\n\n\n\n<p>\u4f5c\u4e3a\u66ff\u4ee3\uff0c\u6211\u4eec\u4e5f\u53ef\u4ee5\u4f7f\u7528\u4ece J6\/3 \u5230 J6\/34 \u8303\u56f4\u5185\u7684\u4efb\u4f55\u5f15\u811a\u6765\u4ee3\u66ffGND \u3002\u53ea\u9700\u8981\u8ba9FPGA \u5c06\u5b83\u4eec\u89c6\u4e3a\u8f93\u51fa\u7ba1\u811a\uff0c\u5e76\u5c06\u5b83\u4eec\u4fdd\u6301\u5728\u903b\u8f91&#8217;0&#8217;\u7535\u5e73 \uff08\u8f93\u51fa\u4f4e\u7535\u5e73\uff09\u3002\u56e0\u6b64\uff0c\u53ef\u4ee5\u5c06\u8fd9\u4e9b\u5f15\u811a\u7528\u4f5cGND\u7684\u529f\u80fd\u3002<\/p>\n\n\n\n<p>\u5f53\u7136\u4e5f\u8fd8\u53ef\u4ee5\u901a\u8fc7\u5c06\u9cc4\u9c7c\u5939\u8fde\u63a5\u5230\u677f\u8fde\u63a5\u5668\u4e4b\u4e00\u7684\u5916\u90e8\u91d1\u5c5e\u90e8\u5206\u6765\u83b7\u5f97\u4e0e ground \u7684\u8fde\u63a5\uff1a Ethernet \u8fde\u63a5\u5668\u3001 HDMI \u8fde\u63a5\u5668\u6216 USB \u8fde\u63a5\u5668\u4e4b\u4e00\uff08\u8fd9\u4e9b\u63a5\u63d2\u4ef6\u7684\u5916\u58f3\u90fd\u662f\u63a5\u5730\u7684\uff09\u3002<\/p>\n\n\n\n<p><strong>PS\uff1a\u5982\u679c\u60f3\u81ea\u5df1\u8bbe\u8ba1\u58f0\u97f3\u8f6c\u63a5\u677f\u7684\uff0c\u4e5f\u53ef\u4ee5\u770b\u672c\u6587\u6700\u540e\u90e8\u5206\uff0c\u6709\u58f0\u97f3\u5b50\u6a21\u5757\u7684\u76f8\u5173\u5185\u5bb9\uff0c\u53ef\u4ee5\u76f4\u63a5\u627ePCB \u677f\u5382\u5bb6\u505a\u677f\u3002<\/strong><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u542f\u52a8\u677f\u5b50<\/strong><\/h2>\n\n\n\n<p>\u50cf\u5f80\u5e38\u4e00\u6837\u6253\u5f00 Smart Zynq \u7535\u6e90\uff08\u6216\u6309\u4e0bPOR\u786c\u4ef6\u590d\u4f4d\u6309\u952e\u8fdb\u884c\u91cd\u542f\uff09\u3002\u4e0b\u4e00\u6b65\u662f\u5bf9FPGA(PL)\u90e8\u5206\u52a0\u8f7d\u7684bitstream\u6587\u4ef6\uff08\u4e0a\u6587\u4e2d\u4fee\u6539\u5e76\u7f16\u8bd1\u7684\u90e8\u5206\uff09\u8fdb\u884c\u9a8c\u8bc1\u3002<\/p>\n\n\n\n<p>\u5728 shell \u547d\u4ee4\u884c\u4e2d\u952e\u5165\u547d\u4ee4\u201chead \/dev\/xillybus_read_32\u201d\u3002\u6b64\u547d\u4ee4\u4ece \/dev\/xillybus_read_32 \u8bfb\u53d6\u7b2c\u4e00\u884c\u5e76\u6253\u5370\u51fa\u7ed3\u679c\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\"># head \/dev\/xillybus_read_32\nPWM\nPWM\nPWM\nPWM\nPWM\nPWM\nPWM\nPWM\nPWM\nPWM<\/pre>\n\n\n\n<p>\u5982\u679c\u6b64\u547d\u4ee4\u6ca1\u6709\u8f93\u51fa\uff0c\u6216\u8005\u8f93\u51fa\u4e0e\u4e0a\u9762\u663e\u793a\u7684\u4e0d\u540c\uff0c\u5219\u8bf4\u660e\u4f7f\u7528\u4e86\u4e0d\u6b63\u786e\u7684 bitstream \u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u64ad\u653e\u97f3\u9891\u6587\u4ef6<\/strong><\/h2>\n\n\n\n<p>\u5c06\u97f3\u9891\u6587\u4ef6\u590d\u5236\u5230 Xillinux\u7684\u6587\u4ef6\u7cfb\u7edf\u4e2d\u3002\u6362\u53e5\u8bdd\u8bf4\uff0c\u97f3\u9891\u6587\u4ef6\u5e94\u9002\u7528\u4e8e Linux \u7cfb\u7edf\u5185\u90e8\u7684\u547d\u4ee4\u3002<strong>\u8be5\u6587\u4ef6\u5e94\u4e3a WAV \u683c\u5f0f\uff1a Uncompressed PCM, 2 channels, s16le \uff08\u8fd9\u51e0\u4e4e\u662f WAV \u6587\u4ef6\u56fa\u5b9a\u7684\u683c\u5f0f\uff09\u3002 \u91c7\u6837\u7387\u5e94\u8be5\u662f 48000 Hz\uff0c\u4f46 44100 Hz \u4e5f\u80fd\u6b63\u5e38\u5de5\u4f5c\u3002<\/strong><\/p>\n\n\n\n<p>\u53ef\u4ee5<a href=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/sample.wav\" data-type=\"link\" data-id=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/sample.wav\">\u4ece\u6b64\u94fe\u63a5<\/a>\u4e0b\u8f7d\u6d4b\u8bd5\u7528\u7684\u97f3\u9891\u6587\u4ef6\u3002<\/p>\n\n\n\n<p>\u6709\u591a\u79cd\u65b9\u6cd5\u53ef\u4ee5\u5c06\u6587\u4ef6\u590d\u5236\u5230 Linux \u7cfb\u7edf\u3002\u4f8b\u5982\uff0c\u53ef\u4ee5\u4f7f\u7528\u4ee5\u592a\u7f51\u901a\u8fc7\u4ee5\u4e0b\u547d\u4ee4\u5c06\u6587\u4ef6\u4ece\u53e6\u4e00\u53f0\u8ba1\u7b97\u673a\u590d\u5236\u5230 Xillinux\u7684 home \u76ee\u5f55 \uff1a$ <strong>scp sample.wav root@192.168.1.10:~\/<\/strong>  \u8fd9\u9002\u7528\u4e8e Microsoft Windows\u3001 command prompt \u4ee5\u53ca Linux shell\u3002\u5c06 IP address \uff08\u672c\u4f8b\u4e2d\u4e3a192.168.1.10 \uff09\u66f4\u6539\u4e3a\u5f53\u524d\u7f51\u7edc\u4e0b\u4e3b\u677f\u7684 IP \u5730\u5740\u3002<strong>(\u53ef\u4ee5\u53c2\u8003 <\/strong><a href=\"http:\/\/www.hellofpga.com\/index.php\/2023\/11\/15\/scp\/\"><strong>Xillinux \u7ae0\u8282\u5341 Windows \u901a\u8fc7 SCP \u547d\u4ee4 \u8fdc\u7a0b\u4f20\u8f93\u6587\u4ef6\u7ed9Xillinux \u7cfb\u7edf<\/strong><\/a>&nbsp;) <\/p>\n\n\n\n<p>\u8fd8\u6709\u5176\u4ed6\u65b9\u6cd5\u53ef\u4ee5\u5c06\u6587\u4ef6\u590d\u5236\u5230 Xillinux \u3002\u4f8b\u5982\uff0c\u4f7f\u7528 NFS \u6216 CIFS\u3002<strong>\uff08CIFS\u670d\u52a1\u5668\u65b9\u5f0f\u53ef\u4ee5\u53c2\u8003 <a href=\"http:\/\/www.hellofpga.com\/index.php\/2023\/12\/10\/cifs2\/\">Xillinux \u7ae0\u8282\u5341\u4e8c \u5728Xillinux \u7cfb\u7edf\u4e0a\u642d\u5efa CIFS\u670d\u52a1(samba)\uff0c\u5b9e\u73b0\u4e0eWindows \u6587\u4ef6\u5171\u4eab<\/a>&nbsp;\uff09<\/strong>\u5982\u679c\u662fCIFS\u65b9\u5f0f\uff0c\u5f53\u524d\u7528\u6237\u76ee\u5f55\u5e94\u8be5\u662f\\root\\root\\    \u5907\u6ce8\u6587\u4ef6\u7cfb\u7edf\u4e2d\u7684\\root\u6587\u4ef6 \u5b9e\u9645\u5728\u8fd9\u91cc\u5e94\u8be5\u662f\\\\192.168.1.10\\root\\root<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"301\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-50-1024x301.png\" alt=\"\" class=\"wp-image-6270\" style=\"width:473px;height:auto\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-50-1024x301.png 1024w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-50-300x88.png 300w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-50-768x225.png 768w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-50.png 1107w\" sizes=\"auto, (max-width: 767px) 89vw, (max-width: 1000px) 54vw, (max-width: 1071px) 543px, 580px\" \/><\/figure>\n\n\n\n<p>\u5c06\u6587\u4ef6\u590d\u5236\u5230 Xillinux\u7684 \u6587\u4ef6\u7cfb\u7edf\u540e<strong>\uff0c<\/strong>\u4f7f\u7528\u4ee5\u4e0b\u547d\u4ee4\u64ad\u653e\u97f3\u9891\uff1a# <strong>cat sample.wav &gt; \/dev\/xillybus_write_32<\/strong>  \uff08\u5c06\u201csample.wav\u201d\u66ff\u6362\u4e3a\u60a8\u8981\u64ad\u653e\u7684\u6587\u4ef6\u7684\u540d\u79f0\u3002\u5982\u679c\u6587\u4ef6\u4f4d\u4e8e\u5f53\u524d\u76ee\u5f55\u4e2d\uff0c\u5219\u6b64\u5904\u663e\u793a\u7684\u547d\u4ee4\u6709\u6548\uff09\u3002<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\"><strong>cat sample.wav &gt; \/dev\/xillybus_write_32<\/strong><\/pre>\n\n\n\n<p>\u8be5\u547d\u4ee4\u5728\u8033\u673a\u4e0a\u64ad\u653e\u6587\u4ef6\uff0c\u76f4\u5230\u64ad\u653e\u5b8c\u6210\u4f1a\u51fa\u73b0\u65b0\u7684 shell prompt  \u3002\u60a8\u5e94\u8be5\u80fd\u591f\u7528\u4e00\u53ea\u8033\u6735\uff08\u6216\u4e24\u53ea\u8033\u6735\uff0c\u5982\u679c\u60a8\u5c06 J6\/1 \u548c J6\/2 \u8fde\u63a5\u5230\u8033\u673a\u63d2\u5934\u7684\u4e0d\u540c\u90e8\u5206\uff09\u542c\u5230\u97f3\u4e50\u3002<\/p>\n\n\n\n<p>\u53ef\u4ee5\u4f7f\u7528 CTRL + C\u4e2d\u9014\u505c\u6b62\u6b64\u547d\u4ee4\uff08\u97f3\u4e50\u64ad\u653e\u547d\u4ee4\uff09\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u5c31\u662f\u8fd9\u6837\u3002\u672c\u9875\u7684\u5176\u4f59\u90e8\u5206\u89e3\u91ca\u4e86\u5176\u5de5\u4f5c\u539f\u7406\u3002<\/strong><\/h2>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u97f3\u9891\u6570\u636e\u5982\u4f55\u5230\u8fbe FPGA<\/strong><\/h2>\n\n\n\n<p>\u201ccat\u201d\u547d\u4ee4\u5c06\u97f3\u9891\u6587\u4ef6 (sample.wav) \u7684\u5185\u5bb9\u590d\u5236\u5230\u540d\u4e3a\u201cxillybus_write_32\u201d\u7684\u8bbe\u5907\u6587\u4ef6\u4e2d\u3002\u5728 Linux \u7cfb\u7edf\u4e2d\uff0c\u8fd9\u662f\u5411 \u786c\u4ef6\u9a71\u52a8\u7a0b\u5e8f\u53d1\u9001\u6570\u636e\u7684\u5e38\u7528\u65b9\u6cd5\u3002\u5728\u6b64\u793a\u4f8b\u4e2d\uff0c \u9a71\u52a8\u7a0b\u5e8f\u4e0e Xillybus\u7684 IP \u6838\u8fde\u63a5\u3002\u6700\u7ec8\u6570\u636e\u88ab\u53d1\u9001\u5230 FPGA\u903b\u8f91\u5185\u90e8\u7684 FIFO \u3002<\/p>\n\n\n\n<p>\u8ba9\u6211\u4eec\u770b\u770b\u4e0a\u9762\u7ed9\u51fa\u7684 Verilog \u4ee3\u7801\u4e2d\u7684\u76f8\u5173\u90e8\u5206\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">fifo_32x512 fifo_32\n     (\n      .clk(bus_clk),\n      \/\/ Interface with Xillybus IP core\n      .srst(!user_w_write_32_open),\n      .din(user_w_write_32_data),\n      .wr_en(user_w_write_32_wren),\n      .full(user_w_write_32_full),\n\n      \/\/ Interface with application logic\n      .rd_en(fifo_rd_en),\n      .dout(fifo_out),\n      .empty(fifo_empty)\n      );<\/pre>\n\n\n\n<p>\u8fd9\u662f\u6807\u51c6 FIFO \u6a21\u5757\u7684\u4f8b\u5316 \u3002\u6709\u5173 FIFO \u5de5\u4f5c\u539f\u7406\u7684\u8bf4\u660e\uff0c\u8bf7\u53c2\u9605<a href=\"https:\/\/www.01signal.com\/zh\/using-ip\/fpga-fifo\/introduction\/\" target=\"_blank\" rel=\"noreferrer noopener\">\u6b64\u9875\u9762<\/a> <strong>\uff08\u9875\u9762\u6765\u81ea 01signal \uff09<\/strong>\u3002<\/p>\n\n\n\n<p>\u8fd9\u4e2a FIFO \u67093\u4e2a\u4e0e\u5411 FIFO\u63d2\u5165\u6570\u636e\u76f8\u5173\u7684\u7aef\u53e3\uff1a din\u3001 wr_en \u548c full\u3002\u6240\u6709\u8fd9\u4e09\u4e2a\u7aef\u53e3\u90fd\u8fde\u63a5\u5230 Xillybus IP\u6838\u3002\u6362\u53e5\u8bdd\u8bf4\uff0c\u4e09\u4e2a\u4fe1\u53f7\uff08user_w_write_32_data\u3001 user_w_write_32_wren \u548c user_w_write_32_full\uff09\u8fde\u63a5\u5230\u540d\u4e3a xillybus\u7684\u6a21\u5757\u3002\u8fd9\u79cd\u8fde\u63a5\u65b9\u5f0f\u5141\u8bb8 Xillybus IP\u6838\u5c06\u6570\u636e\u5199\u5165 FIFO\u3002<\/p>\n\n\n\n<p>Xillybus \u4f7f\u7528\u8fd9\u79cd\u65b9\u6cd5\u5c06\u8f6f\u4ef6\u5199\u5165 \/dev\/xillybus_write_32\u7684\u6570\u636e\u586b\u5145\u5230 FIFO \u3002 Xillybus \u4e0d\u65ad\u5c1d\u8bd5\u5c06\u5c3d\u53ef\u80fd\u591a\u7684\u6570\u636e\u5199\u5165 FIFO\uff0c\u4f46\u5b83\u6c38\u8fdc\u4e0d\u4f1a\u5bfc\u81f4\u6ea2\u51fa\uff08overflow\uff09 \uff08\u5373\u5b83\u9075\u5faaFIFO\u7684 full \u4fe1\u53f7\uff09\u3002 <\/p>\n\n\n\n<p>\u603b\u800c\u8a00\u4e4b\uff0c\u53d1\u751f\u7684\u60c5\u51b5\u662f\u8fd9\u6837\u7684\uff1a<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"970\" height=\"220\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-51.png\" alt=\"\" class=\"wp-image-6272\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-51.png 970w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-51-300x68.png 300w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/02\/image-51-768x174.png 768w\" sizes=\"auto, (max-width: 767px) 89vw, (max-width: 1000px) 54vw, (max-width: 1071px) 543px, 580px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>\u201ccat\u201d\u547d\u4ee4\u5c06\u6570\u636e\u4ece sample.wav \u590d\u5236\u5230 device file\uff08\u8bbe\u5907\u6587\u4ef6\uff09\u3002 \uff08\/dev\/xillybus_write_32\uff09\u3002<\/li>\n\n\n\n<li>Xillybus\u7684\u9a71\u52a8\u7a0b\u5e8f\u5c06\u6b64\u6570\u636e\u590d\u5236\u5230 DMA \u7f13\u51b2\u533a\u4e2d\u3002<\/li>\n\n\n\n<li>FPGA \uff08 Xillybus IP core\uff09\u5185\u90e8\u7684Xillybus\u7684\u903b\u8f91 \u4ece DMA\u7f13\u51b2\u533a\u4e2d\u8bfb\u53d6\u6570\u636e\u5e76\u5c06\u6570\u636e\u5199\u5165 FIFO\u3002<\/li>\n\n\n\n<li>FPGA \u5185\u90e8\u7684\u5e94\u7528\u903b\u8f91\u4ece FIFO \u8bfb\u53d6\u6570\u636e\u5e76\u6d88\u8017\u4f7f\u7528\u8be5\u6570\u636e\u3002<\/li>\n<\/ul>\n\n\n\n<p>\u6240\u6709\u8fd9\u4e9b\u64cd\u4f5c\u90fd\u662f\u540c\u65f6\u8fde\u7eed\u8fdb\u884c\u7684\u3002<\/p>\n\n\n\n<p>\u6709\u5173 Xillybus\u7684\u66f4\u591a\u4fe1\u606f\uff0c\u8bf7\u53c2\u9605<a href=\"https:\/\/www.01signal.com\/zh\/xillybus\/\" target=\"_blank\" rel=\"noreferrer noopener\">\u672c\u7cfb\u5217\u9875\u9762<\/a>\uff0c\u7279\u522b\u662f<a href=\"https:\/\/www.01signal.com\/zh\/xillybus\/data-acquisition\/\" target=\"_blank\" rel=\"noreferrer noopener\">\u672c\u9875\u9762<\/a>\u3002<strong>\uff08\u9875\u9762\u6765\u81ea 01signal\uff09<\/strong><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u97f3\u9891\u4fe1\u53f7\u662f\u5982\u4f55\u521b\u5efa\u7684<\/strong><\/h2>\n\n\n\n<p>\u5230\u76ee\u524d\u4e3a\u6b62\u7684\u63cf\u8ff0\u89e3\u91ca\u4e86\u6570\u636e\u5982\u4f55\u5230\u8fbe FPGA\u5185\u90e8\u7684\u5e94\u7528\u903b\u8f91 \u3002\u73b0\u5728\u6211\u4eec\u5c06\u770b\u770b\u6570\u636e\u5982\u4f55\u8f6c\u6362\u4e3a\u97f3\u9891\u3002<\/p>\n\n\n\n<p>\u9996\u5148\uff0c\u6ce8\u610f Verilog \u4ee3\u7801\u4e2d\u7684\u8fd9\u4e00\u884c\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">assign J6 = { pwm_right, pwm_left };<\/pre>\n\n\n\n<p>\u636e\u6b64\uff0c\u4e24\u4e2a\u97f3\u9891\u8f93\u51fa\u7531 pwm_right \u548c pwm_left\u7ec4\u6210\u3002\u8fd9\u4e24\u4e2a\u5bc4\u5b58\u5668 \u7684\u8d4b\u503c\u5982\u4e0b\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">always @(posedge bus_clk)\n     begin\n\tpwm_level &lt;= pwm_level + 1;\n\n [ ... ]\n\tpwm_left &lt;= (threshold_left &gt; pwm_level);\n\tpwm_right &lt;= (threshold_right &gt; pwm_level);\n [ ... ]\n    end<\/pre>\n\n\n\n<p>\u8bf7\u6ce8\u610f\uff0c pwm_level \u662f\u4e00\u4e2a\u7b80\u5355\u7684\u8ba1\u6570\u5668\u3002\u8be5\u5bc4\u5b58\u5668\u753111\u4f4d\u7ec4\u6210\uff0c\u5e76\u4ece0\u8ba1\u6570\u52302047\uff0c\u7136\u540e\u53c8\u4ece0\u5f00\u59cb\u8ba1\u6570\u3002<\/p>\n\n\n\n<p>\u5f53 threshold_left \u5927\u4e8e pwm_level\u65f6\uff0c pwm_left \u7684\u503c\u4e3a &#8216;1&#8217; \u3002\u6362\u53e5\u8bdd\u8bf4\uff0c threshold_left \u4e0e\u53cd\u590d\u4ece 0 \u5230 2047 \u904d\u5386\u7684\u8ba1\u6570\u5668 pwm_level \u8fdb\u884c\u6bd4\u8f83\u3002 threshold_left \u7684\u503c\u8d8a\u9ad8\uff0c pwm_left \u5177\u6709\u503c &#8216;1&#8217;\u7684\u65f6\u95f4\u5c31\u8d8a\u957f\u3002\u8fd9\u5c31\u662f PWM\u7684\u539f\u7406\uff1a \u8109\u51b2\u7684\u957f\u5ea6\u4e0e\u6211\u4eec\u60f3\u8981\u751f\u6210\u7684\u6a21\u62df\u4fe1\u53f7\u7684\u503c\u6210\u7ebf\u6027\u6bd4\u4f8b\u5173\u7cfb\u3002<\/p>\n\n\n\n<p>pwm_right \u7684\u5de5\u4f5c\u65b9\u5f0f\u4e0e threshold_right\u76f8\u540c\u3002<\/p>\n\n\n\n<p>threshold_left \u548c threshold_right \u5305\u542b\u901a\u8fc7 Xillybus IP \u6838\u53d1\u9001\u7684 WAV \u6587\u4ef6\u4e2d\u7684\u6570\u636e\u3002\u6211\u4eec\u73b0\u5728\u5c06\u8be6\u7ec6\u4e86\u89e3\u8fd9\u662f\u5982\u4f55\u5de5\u4f5c\u7684\u3002<\/p>\n\n\n\n<p>\u9996\u5148\u6211\u4eec\u770b\u4e00\u4e0b FIFO\u7684 \u5b9e\u4f8b \u4e2d\u4e0e\u4ece FIFO\u8bfb\u53d6\u76f8\u5173\u7684\u90e8\u5206\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">\/\/ Interface with application logic\n      .rd_en(fifo_rd_en),\n      .dout(fifo_out),\n      .empty(fifo_empty)<\/pre>\n\n\n\n<p>fifo_rd_en \u5b9a\u4e49\u5982\u4e0b\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\"><strong>wire<\/strong> fifo_rd_en = !fifo_out_valid &amp;&amp; !fifo_empty;<\/pre>\n\n\n\n<p>\u56e0\u6b64\uff0c\u5f53 FIFO \u4e0d\u4e3a\u7a7a\u4e14 fifo_out_valid \u4e3a\u4f4e\u7535\u5e73\u65f6\uff0c FIFO\u7684\u8bfb\u4f7f\u80fd\u4e3a\u9ad8\u7535\u5e73\u3002\u90a3\u4e48\u6211\u4eec\u770b\u4e00\u4e0b fifo_out_valid\u7684\u5b9a\u4e49\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">always @(posedge bus_clk)\n     begin\n [ ... ]\n\tif (fifo_rd_en)\n\t  fifo_out_valid &lt;= 1;\n\telse if (next_word)\n\t  fifo_out_valid &lt;= 0;\n     end<\/pre>\n\n\n\n<p>fifo_out_valid \u7684\u610f\u4e49\u662f\u5f53 FIFO \u8f93\u51fa\u6709\u6548\u65f6\uff0c\u8be5\u5bc4\u5b58\u5668\u4e3a\u9ad8\u7535\u5e73\u3002\u66f4\u51c6\u786e\u5730\u8bf4\uff0c\u5f53 FIFO\u7684\u8f93\u51fa\u5c1a\u672a\u6d88\u8017\u5b8c\u65f6\uff0c fifo_out_valid \u4e3a\u9ad8\u7535\u5e73\u3002\u8fd9\u5c31\u662f\u4e3a\u4ec0\u4e48\u8be5\u5bc4\u5b58\u5668\u5728 fifo_rd_en \u4e3a\u9ad8\u7535\u5e73\u540e\u4e00\u4e2a\u65f6\u949f\u5468\u671f\u53d8\u4e3a\u9ad8\u7535\u5e73\u7684\u539f\u56e0 \u3002\u5f53 next_word \u4e3a\u9ad8\u7535\u5e73\u65f6\uff0c \u8be5\u5bc4\u5b58\u5668\uff08fifo_out_valid\uff09\u53d8\u4e3a\u4f4e\u7535\u5e73\u3002\u6b63\u5982\u6211\u4eec\u5c06\u5728\u4e0b\u9762\u770b\u5230\u7684\uff0c\u5f53 next_word \u4e3a\u9ad8\u7535\u5e73\u65f6\uff0c\u5b9e\u73b0 PWM \u7684\u903b\u8f91\u4f1a\u6d88\u8017 FIFO\u7684\u8f93\u51fa\u3002<\/p>\n\n\n\n<p>next_word \u5b9a\u4e49\u5982\u4e0b\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">wire \tnext_word = (pwm_level == 11'h7ff);<\/pre>\n\n\n\n<p>\u56de\u60f3\u4e00\u4e0b\uff0cpwm_level \u662f\u4e00\u4e2a\u8ba1\u6570\u5668\uff0c\u5b83\u5c06\u904d\u5386 0 \u5230 2047 \u4e4b\u95f4\u7684\u6240\u6709\u503c\u30022047 \u7684\u5341\u516d\u8fdb\u5236\u7f16\u7801\u662f 7ff\u3002\u56e0\u6b64\uff0c\u5728 pwm_level \u5373\u5c06\u56de\u5230\u96f6\u4e4b\u524d\u7684\u90a3\u4e00\u523b\uff0cnext_word \u4e3a\u9ad8\u7535\u5e73\u3002<\/p>\n\n\n\n<p>next_word \u591a\u4e45\u51fa\u73b0\u4e00\u6b21\u9ad8\u7535\u5e73\uff1f bus_clk \u7684\u9891\u7387\u662f 100 MHz\u3002 \u6bcf\u8f6e 2048 \u4e2a\u65f6\u949f\u5468\u671fnext_word \u51fa\u73b0\u9ad8\u7535\u5e73\u4e00\u6b21\u3002 100 MHz \u00f7 2048 \u2248 48828 Hz\u3002\u6240\u4ee5 next_word \u6bcf\u79d2\u5927\u7ea6\u51fa\u73b048828\u6b21\u3002<\/p>\n\n\n\n<p>\u4e4b\u524d\u63d0\u5230\u8fc7\uff0c\u5f53 FIFO\u7684\u8f93\u51fa\u88ab\u6d88\u8017\u65f6\uff0c next_word \u4e3a\u9ad8\u7535\u5e73\u3002\u8fd9\u662f Verilog \u4ee3\u7801\u4e2d\u7684\u76f8\u5173\u90e8\u5206\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">  always @(posedge bus_clk)\n     begin\n [ ... ]\n\n\tif (next_word &amp;&amp; fifo_out_valid)\n\t  begin\n\t     \/\/ The audio samples are signed integers. Change them to\n\t     \/\/ unsigned by adding 1024.\n\t     threshold_left &lt;= fifo_out[15:5] + 1024;\n\t     threshold_right &lt;= fifo_out[31:21] + 1024;\n\t  end\n\telse if (next_word) \/\/ FIFO's output not valid, keep silent\n\t  begin\n\t     threshold_left &lt;= 0;\n\t     threshold_right &lt;= 0;\n\t  end\n [ ... ]\n    end<\/pre>\n\n\n\n<p>\u6211\u4eec\u9996\u5148\u89c2\u5bdf\u5230\uff0c\u5f53 next_word \u4e3a\u9ad8\u7535\u5e73\u65f6\uff0c\u65b0\u503c\u88ab\u5206\u914d\u7ed9 threshold_left \u548c threshold_right\u3002\u5982\u679c fifo_out_valid \u4e3a\u4f4e\u7535\u5e73\uff0c\u5219\u8fd9\u4e24\u4e2a\u5bc4\u5b58\u5668\u7684\u503c\u53d8\u4e3a\u96f6\u3002\u5f53\u6ca1\u6709\u6570\u636e\u53d1\u9001\u5230 FIFO\u65f6\u4f1a\u53d1\u751f\u8fd9\u79cd\u60c5\u51b5\uff0c\u56e0\u6b64\u5b83\u53d8\u4e3a\u7a7a\u3002<\/p>\n\n\n\n<p>\u5982\u679c fifo_out_valid \u4e3a\u9ad8\uff0c\u5219\u610f\u5473\u7740 FIFO\u7684 dout\u7aef\u53e3\u5305\u542b audio sample\uff08\u97f3\u9891\u6837\u672c\uff09\u7684\u503c\u3002\u8be5\u503c\u4ee3\u8868\u4e24\u4e2a\u7acb\u4f53\u58f0\u901a\u9053\u7684\u6a21\u62df\u4fe1\u53f7\u3002\u6bcf\u4e2a\u8fd9\u6837\u7684 sample \u5305\u542b\u4e24\u4e2a\u4ee5 16-bit 2&#8217;s complement \uff08\u5341\u516d\u4f4d\u8865\u7801\u8868\u793a\u6cd5\uff09\u683c\u5f0f\u7ed9\u51fa\u7684\u6709\u7b26\u53f7\u6570\u5b57\u3002<\/p>\n\n\n\n<p>fifo_out[15:0]\u4e2d\u7ed9\u51fa\u4e86\u5c5e\u4e8e\u5de6\u7acb\u4f53\u58f0\u901a\u9053\u7684\u97f3\u9891\u6837\u672c \u3002\u8fd9\u662f\u4e00\u4e2a\u4ecb\u4e8e -32768 \u548c 32767 \u4e4b\u95f4\u7684\u6709\u7b26\u53f7\u6570\u3002\u7a0b\u5e8f\u4e0a\u5220\u9664\u4e86\u4f4e 5 \u4f4d\uff0c\u6240\u4ee5 fifo_out[15:5] \u7684\u8303\u56f4\u4ecb\u4e8e -1024 \u548c 1023 \u4e4b\u95f4\u3002\u56e0\u6b64\uff0c\u8868\u8fbe\u5f0f\u201cfifo_out[15:5] + 1024\u201d\u662f\u4ecb\u4e8e 0 \u548c 2047 \u4e4b\u95f4\u7684\u65e0\u7b26\u53f7\u6570\u3002\u8fd9\u4e2a\u6570\u5b57\u8303\u56f4\u662f\u9002\u5408\u4e0e pwm_level\u8fdb\u884c\u6bd4\u8f83\u3002<\/p>\n\n\n\n<p>\u56e0\u6b64\uff0c\u5f53 fifo_out[15:0] \u7b49\u4e8e -32768 \u65f6\uff0c threshold_left \u5c06\u88ab\u8d4b\u503c\u4e3a\u96f6\u3002\u6761\u4ef6\u201cthreshold_left &gt; pwm_level\u201d\u6c38\u8fdc\u4e0d\u4f1a\u6ee1\u8db3\uff0c\u5219pwm_left \u59cb\u7ec8\u4fdd\u6301\u4f4e\u7535\u5e73\u3002\u53e6\u4e00\u65b9\u9762\uff0c\u5f53 fifo_out[15:0] \u7b49\u4e8e32767\u65f6\uff0c threshold_left\u7684\u503c\u4e3a2047\u3002\u5219pwm_left \u51e0\u4e4e\u4e00\u76f4\u4e3a\u9ad8\u3002\u8fd9\u5c31\u662f fifo_out[15:0] \u63a7\u5236\u6bcf\u4e2a\u8109\u51b2\u4e0a pwm_left \u4e3a\u9ad8\u7535\u5e73\u7684\u65f6\u95f4\u957f\u5ea6\u7684\u65b9\u5f0f\u3002 fifo_out[31:16] \u4ee5\u540c\u6837\u7684\u65b9\u5f0f\u63a7\u5236 pwm_right \u3002<\/p>\n\n\n\n<p>\u603b\u7ed3\u4e00\u4e0b\u6574\u4e2a\u673a\u5236\uff1a next_word \u6bcf 2047 \u4e2a clock cycles\u5c31\u4f1a\u51fa\u73b0\u4e00\u6b21\u9ad8\u7535\u5e73\u3002\u5f53 next_word \u4e3a\u9ad8\u7535\u5e73\u65f6\uff0c FIFO \u7684\u8f93\u51fa\u88ab\u8c03\u6574\u5e76\u590d\u5236\u5230 threshold_left \u548c threshold_right\u4e2d\u3002\u8fd9\u4f1a\u6d88\u8017 FIFO\u7684\u8f93\u51fa\uff0c\u56e0\u6b64 fifo_out_valid \u53d8\u4f4e\u3002\u56e0\u6b64\uff0c\u5982\u679c FIFO \u4e0d\u4e3a\u7a7a\uff0c\u5219 fifo_rd_en \u53d8\u9ad8\uff0c\u4ee5\u4fbf\u4ece FIFO\u8bfb\u53d6\u65b0\u7684 audio sample\uff08\u97f3\u9891\u6837\u672c\uff09 \u3002<\/p>\n\n\n\n<p>\u56de\u60f3\u4e00\u4e0b\uff0c Xillybus IP \u6838\u7528 sample.wav\u7684\u5185\u5bb9\u586b\u5145\u4e86\u8fd9\u4e2a FIFO \u3002\u4e8e\u662f\u5c31\u6709\u4e86\u4e00\u6761\u4ece sample.wav \u7684\u5185\u5bb9\u5230 threshold_left \u3001 threshold_right\u7684 audio samples \u7684\u6570\u636e\u6d41\u3002\u5982\u4e0a\u6240\u8ff0\uff0c next_word \u6bcf\u79d2\u9ad8\u7ea6 48828 \u6b21\u3002\u8fd9\u5c31\u662f\u8fd9\u4e2a\u673a\u5236\u7684 sample rate\uff08\u91c7\u6837\u7387\uff09\u3002<\/p>\n\n\n\n<p>threshold_left \u63a7\u5236 pwm_left \u4e3a\u9ad8\u7535\u5e73\u7684\u65f6\u95f4\u6bd4\u4f8b\u3002 threshold_right \u548c pwm_right\u4e5f\u662f\u5982\u6b64\u3002\u6700\u540e\uff0c pwm_right \u548c pwm_left \u8fde\u63a5\u5230\u540d\u4e3a J6\u7684\u8f93\u51fa\u7aef\u53e3 \uff0c\u56e0\u6b64\u8fd9\u4e9b\u662f\u5f15\u811a\u6392\u9488\u4e0a\u53ef\u89c1\u7684\u4fe1\u53f7\u3002<\/p>\n\n\n\n<p>\u8bf7\u6ce8\u610f\uff0c\u5f53 next_word \u4e3a\u9ad8\u7535\u5e73\u65f6\uff0c\u4f1a\u53d1\u751f\u4e24\u4ef6\u4e8b\uff1a audio sample \uff08\u97f3\u9891\u6837\u672c\uff09\u88ab\u6d88\u8017\uff0c pwm_level \u4ece\u96f6\u5f00\u59cb\u8ba1\u6570\u3002\u56e0\u6b64\uff0c\u6bcf\u4e2a audio sample\u90fd\u4f1a\u751f\u6210\u4e00\u4e2a\u8109\u51b2 \u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u6253\u5370\u51fa\u201cPWM\u201d<\/strong><\/h2>\n\n\n\n<p>\u65e9\u4e9b\u65f6\u5019\uff0c\u6211\u9f13\u52b1\u60a8\u4f7f\u7528\u547d\u4ee4\u201chead \/dev\/xillybus_read_32\u201d\uff0c\u4ee5\u786e\u4fdd FPGA \u52a0\u8f7d\u4e86\u6b63\u786e\u7684 bitstream\uff08\u6bd4\u7279\u6d41\u6587\u4ef6\uff09\u3002\u9884\u671f\u7684\u7ed3\u679c\u662f\u201cPWM\u201d\u88ab\u6253\u5370\u4e86\u5f88\u591a\u6b21\u3002\u8fd9\u90e8\u5206\u5185\u5bb9\u518dVerilog \u4ee3\u7801\u4e2d\u662f\u8fd9\u6837\u5b9e\u73b0\u7684\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">\/\/ Send the text \"PWM\" to reassure that the correct bitstream is used.\n   assign user_r_read_32_eof = 0;\n   assign user_r_read_32_empty = 0;\n   assign user_r_read_32_data = 32'h0a_4d_57_50; \/\/ \"PWM\" + LF<\/pre>\n\n\n\n<p>\u5982\u679c\u60a8\u5728\u8fdb\u884c\u66f4\u6539\u4e4b\u524d\u67e5\u770b xillydemo.v \u6587\u4ef6\uff0c\u60a8\u5c06\u770b\u5230 user_r_read_32_rden\u3001 user_r_read_32_data \u548c user_r_read_32_empty \u5df2\u8fde\u63a5\u5230 FIFO\u3002 Xillybus IP\u6838\u4f7f\u7528\u8fd9\u4e9b\u4fe1\u53f7\u6765\u4ece FIFO \u8bfb\u53d6\u6570\u636e\uff0c\u5e76\u5c06\u5176\u4f5c\u4e3a\u6570\u636e\u6d41\u63d0\u4f9b\u7ed9\u7528\u6237\uff0c\u53ef\u901a\u8fc7<code>\/dev\/xillybus_read_32<\/code>\u8def\u5f84\u8bbf\u95ee\u3002<\/p>\n\n\n\n<p>\u5728 xillydemo.v\u53d1\u751f\u53d8\u5316\u4e4b\u524d\uff0c\u8fd9\u4e9b\u4fe1\u53f7\u8fde\u63a5\u5230 Xillybus IP \u6838\u5199\u5165\u7684\u540c\u4e00\u4e2a FIFO \u3002\u7ed3\u679c\u662f loopback\uff08\u56de\u73af\uff09\uff1a \u8f6f\u4ef6\u5199\u5165 \/dev\/xillybus_write_32 \u7684\u6570\u636e\u9996\u5148\u7531 Xillybus IP \u6838\u63d2\u5165\u5230 FIFO\u961f\u5217\u4e2d \u3002\u7136\u540e\uff0c Xillybus IP \u6838\u518d\u4ece FIFO \u961f\u5217\u8bfb\u53d6\u6570\u636e\u5e76\u5c06\u5176\u4f20\u9012\u7ed9 \/dev\/xillybus_read_32\u3002 loopback \uff08\u56de\u73af\uff09\u7684\u76ee\u7684\u662f\u4e3a\u4e86\u65b9\u4fbf\u5927\u5bb6\u66f4\u597d\u7684\u4ece\u96f6\u5f00\u59cb\u5b66\u4e60\u5e76\u7406\u89e3 Xillybus \u5de5\u4f5c\u539f\u7406\u3002<\/p>\n\n\n\n<p>\u5728xillydemo.v\u66f4\u6539\u540e\uff0c\u8fd9\u4e9b\u4fe1\u53f7\u4e0e FIFO\u65ad\u5f00\u3002\u76f8\u53cd\uff0c user_r_read_32_data \u59cb\u7ec8\u7b49\u4e8e 0x0a4d5750 \uff0c\u800c user_r_read_32_empty \u59cb\u7ec8\u4e3a\u96f6\u3002\u6b64\u5916\uff0c user_r_read_32_rden \u88ab\u903b\u8f91\u5ffd\u7565\u3002\u8fd9\u4f1a\u521b\u5efa\u4e00\u4e2a\u865a\u6784\u7684 FIFO \uff0c\u5b83\u6c38\u8fdc\u4e0d\u4e3a\u7a7a\u3002\u8fd9\u4e2a\u5047\u60f3\u7684 FIFO \u7684\u8f93\u51fa\u59cb\u7ec8\u5177\u6709\u76f8\u540c\u7684\u503c\uff1a 0x0a4d5750\u3002 Xillybus IP\u6838\u7684\u884c\u4e3a\u5c31\u597d\u50cf\u6709\u4e00\u4e2a\u59cb\u7ec8\u5145\u6ee1\u6b64\u5e38\u91cf\u503c\u7684FIFO\u3002\u56e0\u6b64\uff0c\u5f53\u4ece \/dev\/xillybus_read_32\u8bfb\u53d6\u65f6\uff0c\u5b57 0x0a4d5750 \u4f1a\u91cd\u590d\u5230\u8fbe\u3002\u5f53\u8fd9\u4e2a\u5b57\u88ab\u6253\u5370\u51fa\u6765\u65f6\uff0c\u5b83\u88ab\u89e3\u91ca\u4e3a\u56db\u4e2a\u5b57\u8282\uff1a 0x50\u3001 0x57\u3001 0x4d \u548c 0x0a\u3002\u6362\u53e5\u8bdd\u8bf4\uff0c\u5b57\u7b26 P\u3001 W\u3001 M \u548c \u6362\u884c\u7b26\uff08\u5728 Linux \u4e2d\u7528\u4e8e\u6807\u8bb0\u884c\u7684\u7ed3\u5c3e\uff09\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Verilog \u4ee3\u7801\u4e0e\u771f\u5b9e\u5f15\u811a\u7684\u5173\u7cfb<\/strong><\/h2>\n\n\n\n<p>\u4e0a\u9762\u7684 Verilog \u4ee3\u7801\u5c06 PWM \u4fe1\u53f7\u8fde\u63a5\u5230 J6\uff0c\u4f46\u662f\u8fd9\u662f\u5982\u4f55\u5230\u8fbe\u5f15\u811a\u63a5\u63d2\u4ef6\u4e0a\u7684\u5462\uff1f\u7b54\u6848\u53ef\u4ee5\u5728 xillydemo.xdc\u4e2d\u627e\u5230\u3002\u8be5\u6587\u4ef6\u662f\u521b\u5efa bitstream \u7684 Vivado \u9879\u76ee\u7684\u4e00\u90e8\u5206\uff08\u4f4d\u4e8e\u201cvivado-essentials\u201d\u76ee\u5f55\u4e2d\uff09\u3002<\/p>\n\n\n\n<p>xillydemo.xdc \u5305\u542b FPGA \u4f5c\u4e3a\u7535\u5b50\u5143\u4ef6\u6b63\u5e38\u5de5\u4f5c\u6240\u9700\u7684\u5404\u79cd\u4fe1\u606f\u3002\u5176\u4e2d\uff0c\u8be5\u6587\u4ef6\u5305\u542b\u4ee5\u4e0b\u884c\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">[ ... ] \n\n## \u8239\u4e0a J6 (BANK33 VADJ) \nset_property PACKAGE_PIN U22   [get_ports { J6[0] }] ; #J6\/1 = IO_B33_LN2 \nset_property PACKAGE_PIN T22 [get_ports {J6[ 1 ]}] ; #J6\/2 = IO_B33_LP2 \nset_property PACKAGE_PIN W22 [get_ports {J6[ 2 ]}] ; #J6\/3 = IO_B33_LN3 \nset_property PACKAGE_PIN V22 [get_ports {J6[ 3 ]}] ; #J6\/4 = IO_B33_LP3 \nset_property PACKAGE_PIN Y21 [get_ports {J6[ 4 ]}] ; #J6\/5 = IO_B33_LN9 \nset_property PACKAGE_PIN Y20 [get_ports {J6[ 5 ]}] ; #J6\/6 = IO_B33_LP9 \nset_property PACKAGE_PIN AB22 [get_ports {J6[ 6 ]}] ; #J6\/7 = IO_B33_LN7 \nset_property PACKAGE_PIN AA22 [get_ports {J6[ 7 ]}] ; #J6\/8 = IO_B33_LP7 \n\n[ ... ]<\/pre>\n\n\n\n<p>\u7b2c\u4e00\u884c\u8868\u793a\u4fe1\u53f7 J6[0] \u5e94\u8fde\u63a5\u5230 U22\u3002\u8fd9\u662f FPGA\u7269\u7406\u5c01\u88c5\u4e0a\u7684\u4f4d\u7f6e\u3002\u6839\u636e Smart Zynq\u7684 \u539f\u7406\u56fe\uff0c\u8fd9\u4e2a FPGA\u5f15\u811a\u8fde\u63a5\u5230J6\u6392\u9488\u7684\u7b2c\u4e00\u4e2a\u5f15\u811a\u4e0a \u3002\u5176\u4ed6\u7aef\u53e3\u7684\u4f4d\u7f6e\u4e5f\u4ee5\u540c\u6837\u7684\u65b9\u5f0f\u5b9a\u4e49\u3002<\/p>\n\n\n\n<p>\u6211\u4e0a\u9762\u63d0\u5230\uff0c\u4ece J6\/3 \u5230 J6\/34 \u8303\u56f4\u5185\u7684\u4efb\u4f55\u5f15\u811a\u90fd\u53ef\u4ee5\u7528\u4f5c\u63a5\u5730\uff0c\u56e0\u4e3a\u8fd9\u4e9b\u8f93\u51fa\u5f15\u811a\u7684\u503c\u4e3a\u201c0\u201d\u3002\u8fd9\u662f\u6b63\u786e\u7684\uff0c\u56e0\u4e3a\u6839\u636e xillydemo.v \u5f00\u5934\u7684\u8fd9\u4e00\u884c\uff0cJ6 \u7531 34 \u4f4d\u7ec4\u6210\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\"> inout [33:0] J6,  \/\/BANK33 VADJ<\/pre>\n\n\n\n<p>\u56de\u60f3\u4e00\u4e0b J6 \u7684\u8d4b\u503c\u5982\u4e0b\uff1a<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">assign J6 = { pwm_right, pwm_left };<\/pre>\n\n\n\n<p>\u8fd9\u610f\u5473\u7740 J6[0] \u7b49\u4e8e pwm_left \uff0c J6[1] \u7b49\u4e8e pwm_right\u3002\u5269\u4e0b\u7684\u5462\uff1f\u6839\u636e Verilog\u7684\u8bed\u6cd5\uff0c\u6240\u6709\u5176\u4ed6\u4f4d\u90fd\uff08\u9ed8\u8ba4\uff09\u88ab\u5206\u914d\u4e3a\u96f6\u503c\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>DC bias<\/strong>\uff08\u76f4\u6d41\u504f\u7f6e\u7535\u538b\uff09<\/h2>\n\n\n\n<p>\u6392\u9488\u8fde\u63a5\u5230 FPGA\u7684\u903b\u8f91\u8f93\u51fa\u3002\u5f53\u903b\u8f91\u72b6\u6001\u8f93\u51fa\u662f &#8216;1&#8217;\u65f6\uff0c\u8fd9\u4e9b\u5f15\u811a\u4e2d\u7684\u6bcf\u4e00\u4e2a\u7684\u7535\u538b\u90fd\u5728 3.3V \u5de6\u53f3\u3002\u5f53\u903b\u8f91\u72b6\u6001\u8f93\u51fa\u4e3a &#8216;0&#8217;\u65f6\uff0c\u7535\u538b\u5728 0V\u5de6\u53f3\u3002<\/p>\n\n\n\n<p>\u5982\u679c\u539f\u59cb\u97f3\u9891\u6837\u672c\u91c7\u6837\u7684\u503c\u4e3a0\uff0c\u5219 threshold_left \u548c threshold_right \u7684\u503c\u4e3a1024\u3002\u6362\u53e5\u8bdd\u8bf4\uff0c\u5e73\u5747\u800c\u8a00\uff0c pwm_right \u548c pwm_left \u5c06\u5728\u4e00\u534a\u7684\u65f6\u95f4\u5185\u5904\u4e8e\u9ad8\u7535\u5e73\u3002\u56e0\u6b64\u5e73\u5747\u7535\u538b (DC) \u4e3a 3.3V \u00f7 2 = 1.65V\u3002\u6240\u4ee5\u5373\u4f7f WAV \u6587\u4ef6\u4e2d\u7684\u97f3\u9891\u6837\u672c\u5177\u6709\u4e00\u4e2a\u5b8c\u7f8e\u7684\u76f4\u6d41\u5e73\u8861\uff08 DC balance\uff09\uff0c\u8033\u673a\u4e5f\u4f1a\u66b4\u9732\u5728 1.65V \u7684\u76f4\u6d41\u5206\u91cf\u4e0b\u3002<\/p>\n\n\n\n<p>\u56e0\u6b64\uff0c \u5916\u63a550\u03a9-200\u03a9\u7535\u963b\u7684\u76ee\u7684\u4e0d\u4ec5\u662f\u964d\u4f4e\u58f0\u7ea7\uff0c\u800c\u4e14\u662f\u9650\u5236\u76f4\u6d41\u7535\u6d41\u3002\u4f46\u5373\u4f7f\u6ca1\u6709\u8fd9\u4e2a\u7535\u963b\uff0c\u7531\u4e8e FPGA\u81ea\u8eab\u9a71\u52a8\u80fd\u529b\u7684\u9650\u5236\u548c\u8033\u673a\u81ea\u8eab\u7684\u7ebf\u5708\u7535\u963b\uff0c\u7535\u6d41\u4e5f\u53ef\u80fd\u662f\u65e0\u5bb3\u7684\u3002\u7535\u963b\u53ea\u662f\u4e00\u79cd\u9884\u9632\u63aa\u65bd\u3002<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u6982\u62ec<\/strong><\/h2>\n\n\n\n<p>\u8be5\u9879\u76ee\u5c55\u793a\u4e86\u5982\u4f55\u4f7f\u7528\u6570\u5b57\u8f93\u51fa\u5f15\u811a\u6765\u751f\u6210\u53ef\u76f4\u63a5\u8fde\u63a5\u5230\u8033\u673a\u7684\u6a21\u62df\u97f3\u9891\u4fe1\u53f7\u3002\u8be5\u9879\u76ee\u7684\u91cd\u70b9\u662f\u5c55\u793a\u5982\u4f55\u4f7f\u7528 Xillybus stream \u5c06\u6570\u636e\u4ece\u8f6f\u4ef6\u53d1\u9001\u5230 FPGA\u3002\u8fd8\u5c55\u793a\u4e86 PWM \u7684\u7b80\u5355\u5b9e\u73b0\u3002<\/p>\n\n\n\n<p><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>\u58f0\u97f3\u5b50\u6a21\u5757<\/strong><\/h2>\n\n\n\n<p>\u524d\u9762\u4ecb\u7ecd\u7684\u8fde\u63a5\u65b9\u6cd5\u662f\u7528\u4e86\u9cc4\u9c7c\u5939\u7684\u8fde\u63a5\u7684\u65b9\u5f0f\uff0c\u4e3a\u4e86\u65b9\u4fbf\u6f14\u793a\uff0c\u8fd9\u91cc\u4e5f\u7b80\u5355\u753b\u4e86\u4e00\u4e2a\u58f0\u97f3\u5b50\u6a21\u5757\uff0c\u6574\u4e2a\u6210\u672c\u4e0b\u6765\u4e0d\u8d85\u8fc72\u4eba\u6c11\u5e01\uff0c\u5927\u5bb6\u6709\u5174\u8da3\u7684\u53ef\u4ee5\u81ea\u5df1\u505a\u677f\u710a\u63a5\u8c03\u8bd5\uff08\u6587\u4ef6\u91cc\u7684gerber \u538b\u7f29\u5305\u53ef\u4ee5\u76f4\u63a5\u6295\u677f\u5382\u505a\u677f\uff09\u3002<\/p>\n\n\n\n<p>\u58f0\u97f3\u5b50\u6a21\u5757\u4e0b\u8f7d\u5730\u5740\u5982\u4e0b\uff1a\uff08\u677f\u5b50\u4e0a\u6709\u4e24\u4e2a0603\u7684\u7535\u963b\uff0c\u5bf9\u624b\u5de5\u710a\u63a5\u80fd\u529b\u6709\u4e00\u70b9\u8981\u6c42\uff09<\/p>\n\n\n\n<div class=\"wp-block-file\"><a id=\"wp-block-file--media-ef05742d-c5c7-4737-a2f6-e7452b304119\" href=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/Sound_Module_20240302.zip\">Sound_Module_20240302<\/a><a href=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/Sound_Module_20240302.zip\" class=\"wp-block-file__button wp-element-button\" download aria-describedby=\"wp-block-file--media-ef05742d-c5c7-4737-a2f6-e7452b304119\">\u4e0b\u8f7d<\/a><\/div>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"680\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-2-1024x680.png\" alt=\"\" class=\"wp-image-6319\" style=\"width:512px;height:auto\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-2-1024x680.png 1024w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-2-300x199.png 300w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-2-768x510.png 768w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-2.png 1071w\" sizes=\"auto, (max-width: 767px) 89vw, (max-width: 1000px) 54vw, (max-width: 1071px) 543px, 580px\" \/><\/figure>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"787\" height=\"583\" src=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-1.png\" alt=\"\" class=\"wp-image-6321\" style=\"width:516px;height:auto\" srcset=\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-1.png 787w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-1-300x222.png 300w, http:\/\/www.hellofpga.com\/wp-content\/uploads\/2024\/03\/image-1-768x569.png 768w\" sizes=\"auto, (max-width: 767px) 89vw, (max-width: 1000px) 54vw, (max-width: 1071px) 543px, 580px\" \/><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>\u672c\u6559\u7a0b\u4ecb\u7ecd\u5982\u4f55\u5c06\u666e\u901a\u8033\u673a\u8fde\u63a5\u5230 Smart Zynq \u677f\u5e76\u542c\u97f3\u4e50\u3002\u8be5\u9879\u76ee\u7684\u76ee\u7684\u662f\u6f14\u793a\u5982\u4f55\u4f7f\u7528 Xillybus stream \u5411 FPGA\u53d1\u9001\u8fde\u7eed\u6570\u636e\u3002\u6b64\u5904\u8fd8\u663e\u793a\u4e86\u5b9e\u73b0 PWM modulator \u7684 Verilog \u4ee3\u7801\u3002<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[21],"tags":[],"class_list":["post-6145","post","type-post","status-publish","format-standard","hentry","category-xillinux"],"views":1099,"_links":{"self":[{"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/posts\/6145","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/comments?post=6145"}],"version-history":[{"count":71,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/posts\/6145\/revisions"}],"predecessor-version":[{"id":8647,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/posts\/6145\/revisions\/8647"}],"wp:attachment":[{"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/media?parent=6145"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/categories?post=6145"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.hellofpga.com\/index.php\/wp-json\/wp\/v2\/tags?post=6145"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}