\u4e00\u3001\u5173\u4e8eUART<\/strong><\/h2>\n\n\n\n\u4ec0\u4e48\u662fUART<\/strong><\/h3>\n\n\n\nUART\u662f\u4e00\u79cd\u4e32\u884c\u901a\u4fe1\u534f\u8bae\uff0c\u7528\u4e8e\u5728\u8bbe\u5907\u4e4b\u95f4\u4f20\u8f93\u6570\u636e\u3002\u5b83\u901a\u5e38\u7528\u4e8e\u8fde\u63a5\u8ba1\u7b97\u673a\u4e0e\u5916\u90e8\u8bbe\u5907\uff08\u6bd4\u5982\u4f20\u611f\u5668\u3001\u663e\u793a\u5668\u3001\u6a21\u5757\u7b49\uff09\u3002<\/p>\n\n\n\n
UART\u4e0d\u50cf\u5176\u4ed6\u534f\u8bae\uff08\u6bd4\u5982SPI\u6216I2C\uff09\u9700\u8981\u540c\u6b65\u65f6\u949f\u4fe1\u53f7\uff0c\u56e0\u6b64\u88ab\u79f0\u4e3a\u5f02\u6b65\u534f\u8bae\u3002\u8fd9\u610f\u5473\u7740\u53d1\u9001\u548c\u63a5\u6536\u8bbe\u5907\u4e0d\u9700\u8981\u5171\u4eab\u540c\u6b65\u65f6\u949f\u3002\u6bcf\u4e2a\u8bbe\u5907\u6709\u81ea\u5df1\u7684\u65f6\u949f\uff0c\u5e76\u4e14\u901a\u8fc7\u8d77\u59cb\u4f4d\u6765\u540c\u6b65\u6570\u636e\u4f20\u8f93\u3002<\/p>\n\n\n\n
UART\u7684\u534f\u8bae\u6784\u6210\uff1a<\/strong><\/h3>\n\n\n\n\n- \u8d77\u59cb\u4f4d\uff08Start Bit\uff09<\/strong>\uff1a\u6307\u793a\u6570\u636e\u4f20\u8f93\u5f00\u59cb\u7684\u4f4d\u3002\u5b83\u662f\u903b\u8f91\u4f4e\u7535\u5e73\uff080\uff09\uff08\u603b\u7ebf\u7a7a\u95f2\u65f6\u4e3a\u9ad8\u7535\u5e73\uff0c\u6240\u4ee5\u5f00\u59cb\u901a\u4fe1\u65f6\u5148\u53d1\u9001\u4e00\u4e2a\u533a\u522b\u4e8e\u7a7a\u95f2\u72b6\u6001\u7684\u4fe1\u53f7\uff0c\u8d77\u59cb\u4f4d\u4e5f\u4f5c\u65f6\u949f\u540c\u6b65\u7528\uff09<\/li>\n\n\n\n
- \u6570\u636e\u4f4d\uff08Data Bits\uff09<\/strong>\uff1a\u5305\u542b\u8981\u4f20\u8f93\u7684\u6570\u636e\uff0c\u901a\u5e38\u4e3a8\u4f4d\uff0c\u5148\u53d1\u9001\u6570\u636e\u7684\u6700\u4f4e\u4f4d\uff0c\u6700\u540e\u53d1\u9001\u6570\u636e\u7684\u6700\u9ad8\u4f4d\uff0c<\/li>\n\n\n\n
- \u5947\u5076\u6821\u9a8c\u4f4d\uff08Parity Bit\uff09<\/strong>\uff08\u53ef\u9009\uff09\uff1a\u7528\u4e8e\u6570\u636e\u6821\u9a8c\uff0c\u6709\u5947\u5076\u4e24\u79cd\u7c7b\u578b\uff0c\u6709\u65f6\u7528\u4e8e\u68c0\u6d4b\u4f20\u8f93\u4e2d\u7684\u9519\u8bef\u3002<\/li>\n\n\n\n
- \u505c\u6b62\u4f4d\uff08Stop Bit\uff09<\/strong>\uff1a\u6807\u5fd7\u6570\u636e\u4f20\u8f93\u7ed3\u675f\u7684\u4f4d\uff0c\u901a\u5e38\u662f\u903b\u8f91\u9ad8\u7535\u5e73\uff081\uff09<\/li>\n\n\n\n
- \u7a7a\u95f2\u65f6\u6bb5<\/strong>\uff1aUART\u534f\u8bae\u89c4\u5b9a\uff0c\u5f53\u603b\u7ebf\u5904\u4e8e\u7a7a\u95f2\u72b6\u6001\u65f6\u4fe1\u53f7\u7ebf\u7684\u72b6\u6001\u4e3a\uff081\uff09<\/li>\n<\/ul>\n\n\n\n
\u4e5f\u5c31\u662f\u5982\u679c\u6211\u4eec\u89c2\u5bdfUART\u6ce2\u5f62\u53ef\u4ee5\u770b\u5230\u5728\u6ca1\u6709\u901a\u8baf\u7684\u65f6\u5019\uff0cUART\u4fe1\u53f7\u7ebf\u662f\u662f\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u5373\u7a7a\u95f2\u72b6\u6001\uff09\uff0c\u5f53\u4e00\u4e2a\u4e0b\u964d\u6cbf\u4e8b\u4ef6\u53d1\u751f\u65f6\uff0c\u6211\u4eec\u8ba4\u4e3a\u5c06\u8fdb\u884c\u4e00\u6b21\u6570\u636e\u7684\u4f20\u8f93\u3002<\/p>\n\n\n\n![\"\"](\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2025\/04\/image-9-1024x556.png\")
<\/figure>\n\n\n\n\u4e24\u4e2a\u8bbe\u5907\u8981\u7528UART\u8fdb\u884c\u901a\u8baf\uff0cTX\u548cRX\u4e24\u4e2a\u4fe1\u53f7\u7ebf\u662f\u9700\u8981\u4ea4\u53c9\u7684\uff0c\u9664\u4e86TX\u548cRX\u4fe1\u53f7\u5916\uff0c\u4e24\u4e2a\u8bbe\u5907\u95f4\u8fd8\u9700\u8981\u5171\u5730(GND)\u3002<\/p>\n\n\n\n![\"\"](\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2025\/04\/image-10-1024x282.png\")
<\/figure>\n\n\n\nUART \u901a\u8baf\u7535\u5e73<\/strong><\/h2>\n\n\n\n\n- UART\u7684\u7535\u5e73\uff0c\u5176\u5b9e\u662f\u6709\u4e24\u79cd\u89c4\u683c\u7684\uff0c\u4e24\u8005\u7535\u538b\u4e0d\u540c\uff0c\u903b\u8f91\u4e5f\u76f8\u53cd\uff0c\u4e0d\u80fd\u76f4\u63a5\u8fde\u63a5<\/strong>\n
\n- RS232 <\/strong>( \u00b112V, \u5176\u4e2d+12V\u4ee3\u8868\u903b\u8f911\uff0c-12V\u4ee3\u8868\u903b\u8f910) \u591a\u7528\u4e8e\u8001\u5f0f\u7535\u8111\u4e32\u53e3\u548c\u5de5\u4e1a\u8bbe\u5907\u7684\u901a\u8baf<\/li>\n\n\n\n
- TTL232<\/strong>\uff083.3V\/5V\u4ee3\u8868\u903b\u8f911\uff0c 0V\u4ee3\u8868\u903b\u8f910\uff09\u5e38\u7528\u4e8e\u5355\u7247\u673a\u3001\u5f00\u53d1\u677f\u7b49\u5d4c\u5165\u5f0f\u7cfb\u7edf<\/li>\n\n\n\n
- RS232\u548cTTL232\u53ef\u901a\u8fc7\u4e13\u7528\u82af\u7247\u8fdb\u884c\u8f6c\u6362\uff0c\u5982\uff08MAX232\u82af\u7247\u7b49\uff09<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
\u4e8c\u3001\u5de5\u7a0b\u521b\u5efa\uff1a<\/strong><\/h2>\n\n\n\n\u5de5\u7a0b\u521b\u5efa\u7684\u8fc7\u7a0b\u53ef\u4ee5\u53c2\u8003\u5b9e\u9a8c\u4e00\u4e2d\u7684\u5185\u5bb9\uff0c\u8fd9\u91cc\u4e0d\u8be6\u7ec6\u63cf\u8ff0\u4e86\u3002<\/a>\u57fa\u4e8eSmart Artix \u7684FPGA\u5b9e\u9a8c\u4e00 \u7528FPGA\u8d44\u6e90\u70b9\u4eae\u4e00\u4e2aLED\uff08\u5b8c\u6574\u56fe\u6587\uff09<\/a> (\u82af\u7247\u578b\u53f7\u9009XC7A50TFGG484-2)<\/strong><\/p>\n\n\n\n\u5b9e\u9a8c\u5185\u5bb9\uff1a<\/strong><\/h2>\n\n\n\n\n- \u672c\u6b21\u5b9e\u9a8c\u6211\u4eec\u5c06\u8bbe\u8ba1\u4e00\u4e2a\u7b80\u5355\u7684UART\u6a21\u5757\uff0c\u5177\u4f53\u529f\u80fd\u5982\u4e0b\uff1a<\/strong>\n
\n- \u4e0a\u7535\u540e\uff0c\u4e32\u53e3\u81ea\u52a8\u53d1\u9001\u5b57\u7b26\u4e32\uff1a
hellofpga.com<\/code><\/strong><\/li>\n\n\n\n- \u53d1\u9001\u5b8c\u6210\u540e\uff0c\u8fdb\u5165\u56de\u73af\u6a21\u5f0f<\/strong>\uff1a\u4e32\u53e3\u63a5\u6536\u7684\u6570\u636e\u76f4\u63a5\u539f\u6837\u8fd4\u56de\u53d1\u9001\uff08Loopback\uff09<\/li>\n\n\n\n
- \u4e32\u53e3\u6a21\u5757\u7cfb\u7edf\u65f6\u949f50M\uff0c\u6ce2\u7279\u7387115200\uff0c8 \u4f4d\u6570\u636e\uff0c\u65e0\u6821\u9a8c\uff0c1 \u4f4d\u505c\u6b62\u4f4d\uff088N1\uff09<\/li>\n<\/ul>\n<\/li>\n\n\n\n
- \u5de5\u7a0b\u5c06\u5206\u4e3a3\u4e2a\u6a21\u5757\u6765\u8fdb\u884c\u8bbe\u8ba1\uff1a<\/strong>\n
\n- \u9876\u5c42\u6a21\u5757
uart_top.v<\/code><\/strong>\uff08\u521d\u59cb\u5316\u65f6\u53d1\u9001\u5b57\u7b26\u4e32 \"hellofpga.com\"<\/code>\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff09<\/li>\n\n\n\n- \u4e32\u53e3\u53d1\u9001\u6a21\u5757
uart_tx.v<\/code><\/strong>\uff08\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff09<\/li>\n\n\n\n- \u4e32\u53e3\u63a5\u6536\u6a21\u5757
uart_rx.v<\/code><\/strong>\uff08\u5bf9\u8f93\u5165\u7684 RX \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff09<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\na) \u521b\u5efa\u4e00\u4e2a\u9876\u5c42\u6a21\u5757\uff08uart_top.v<\/code>\uff09<\/strong><\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_top(
input wire clk,
input wire rst_n,
input wire rx,
output wire tx
);
localparam INIT = 2'd0;
localparam SENDING = 2'd1;
localparam LOOP = 2'd2;
reg [1:0] state = INIT;
reg start_tx = 0;
reg [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire rx_done;
reg [3:0] send_index = 0;
reg [7:0] send_buf [12:0];
reg [7:0] tx_buf;
reg tx_req;
initial begin
send_buf[0] = \"h\";
send_buf[1] = \"e\";
send_buf[2] = \"l\";
send_buf[3] = \"l\";
send_buf[4] = \"o\";
send_buf[5] = \"f\";
send_buf[6] = \"p\";
send_buf[7] = \"g\";
send_buf[8] = \"a\";
send_buf[9] = \".\";
send_buf[10] = \"c\";
send_buf[11] = \"o\";
send_buf[12] = \"m\";
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= INIT;
send_index <= 0;
start_tx <= 0;
tx_req <= 0;
end else begin
case (state)
INIT: begin
state <= SENDING;
send_index <= 0;
end
SENDING: begin
if (!tx_busy && !start_tx && send_index < 13) begin
tx_data <= send_buf[send_index];
start_tx <= 1;
send_index <= send_index + 1;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end else if (send_index >= 13 && !tx_busy) begin
state <= LOOP;
end
end
LOOP: begin
if (rx_done && !tx_req) begin
tx_buf <= rx_data;
tx_req <= 1;
end
if (tx_req && !tx_busy && !start_tx) begin
tx_data <= tx_buf;
start_tx <= 1;
tx_req <= 0;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end
end
endcase
end
end
uart_tx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_tx (
.clk(clk),
.rst_n(rst_n),
.tx_data(tx_data),
.tx_start(start_tx),
.tx(tx),
.tx_busy(tx_busy)
);
uart_rx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_rx (
.clk(clk),
.rst_n(rst_n),
.rx(rx),
.rx_data(rx_data),
.rx_done(rx_done)
);
endmodule<\/pre>\n\n\n\nUART \u9876\u5c42\u6a21\u5757\u5728\u7cfb\u7edf\u542f\u52a8\u65f6\uff0c\u4f1a\u5148\u901a\u8fc7\u4e32\u53e3\u53d1\u9001\u4e00\u4e32\u5b57\u7b26\u4e32 \u201chellofpga.com\u201d\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\u3002\u6240\u8c13\u56de\u73af\u6a21\u5f0f\uff0c\u5c31\u662f\u6536\u5230\u4ec0\u4e48\u6570\u636e\uff0c\u5c31\u7acb\u5373\u4ece TX \u53d1\u56de\u53bb\uff0c\u5b9e\u73b0 UART \u7684\u6570\u636e\u56de\u9001\u529f\u80fd\uff0c\u65b9\u4fbf\u6d4b\u8bd5\u4e32\u53e3\u662f\u5426\u6b63\u5e38\u3002<\/p>\n\n\n\n
\u6574\u4e2a\u6a21\u5757\u5206\u4e3a\u4e09\u4e2a\u72b6\u6001\uff1a\u521d\u59cb\u5316\uff08INIT\uff09\u3001\u53d1\u9001\u56fa\u5b9a\u5b57\u7b26\u4e32\uff08SENDING\uff09\u548c\u56de\u73af\uff08LOOP\uff09\u3002\u4e3a\u907f\u514d\u53d1\u9001\u51b2\u7a81\uff0c\u56de\u73af\u90e8\u5206\u52a0\u5165\u4e86\u4e00\u4e2a\u53d1\u9001\u8bf7\u6c42\u6807\u5fd7 tx_req<\/code>\uff0c\u786e\u4fdd\u63a5\u6536\u6570\u636e\u540e\u4e0d\u4f1a\u4e22\u5305\u3002\u53d1\u9001\u548c\u63a5\u6536\u7684\u6ce2\u7279\u7387\u3001\u65f6\u949f\u9891\u7387\u90fd\u53ef\u901a\u8fc7\u53c2\u6570\u914d\u7f6e\uff0c\u4fbf\u4e8e\u7075\u6d3b\u4fee\u6539\u3002\uff08tx_req<\/code> \u662f\u4e00\u4e2a \u201c\u53d1\u9001\u51c6\u5907\u6807\u5fd7\u201d<\/strong>\uff0c\u8868\u793a\u5df2\u7ecf\u6536\u5230\u6570\u636e\u4f46\u8fd8\u6ca1\u53d1\u9001\u51fa\u53bb\uff0c\u7b49\u5230\u53d1\u9001\u6a21\u5757\u7a7a\u95f2\u65f6\u518d\u542f\u52a8\u53d1\u9001\uff0c\u9632\u6b62\u6570\u636e\u51b2\u7a81\u6216\u9057\u6f0f\uff09<\/p>\n\n\n\nb) \u521b\u5efa\u4e32\u53e3\u53d1\u9001\u6a21\u5757 (uart_tx.v<\/code><\/strong>)<\/p>\n\n\n\n\u529f\u80fd\uff1a\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff0c\uff08tx_start<\/code> \u62c9\u9ad8\u5f00\u59cb\u53d1\u9001\uff0c\u53d1\u9001\u671f\u95f4tx_busy<\/code> \u4e3a\u9ad8\u8868\u793a\u5f53\u524d\u6b63\u5728\u53d1\u9001\uff09<\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_tx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire [7:0] tx_data,
input wire tx_start,
output reg tx,
output reg tx_busy
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_idx = 0;
reg [9:0] tx_shift = 10'b1111111111;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx <= 1;
tx_busy <= 0;
baud_cnt <= 0;
bit_idx <= 0;
tx_shift <= 10'b1111111111;
end
else begin
if (tx_start && !tx_busy) begin
tx_shift <= {1'b1, tx_data, 1'b0};
tx_busy <= 1;
baud_cnt <= 0;
bit_idx <= 0;
end
else if (tx_busy) begin
if (baud_cnt == BAUD_TICK - 1) begin
baud_cnt <= 0;
tx <= tx_shift[bit_idx];
bit_idx <= bit_idx + 1;
if (bit_idx == 9) begin
tx_busy <= 0;
tx <= 1;
end
end
else begin
baud_cnt <= baud_cnt + 1;
end
end
end
end
endmodule<\/pre>\n\n\n\n\u5f53 tx_start<\/code> \u4fe1\u53f7\u4e3a\u9ad8\u5e76\u4e14\u5f53\u524d\u53d1\u9001\u5668\u7a7a\u95f2\u65f6\uff0c\u6a21\u5757\u5c06\u6570\u636e\u6253\u5305\u6210 10 \u4f4d\u53d1\u9001\u5e27\uff08\u8d77\u59cb\u4f4d + \u6570\u636e + \u505c\u6b62\u4f4d\uff09\uff0c\u5e76\u5f00\u59cb\u4ee5\u56fa\u5b9a\u6ce2\u7279\u7387\uff08\u7531 CLK_FREQ<\/code> \u4e0e BAUD_RATE<\/code> \u53c2\u6570\u51b3\u5b9a\uff09\u9010\u4f4d\u8f93\u51fa\u5230 tx<\/code>\u3002\u53d1\u9001\u8fc7\u7a0b\u4e2d\uff0ctx_busy<\/code> \u4f1a\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u8868\u793a\u53d1\u9001\u5668\u6b63\u5fd9\uff09\uff0c\u76f4\u5230\u6240\u6709\u4f4d\u5b8c\u6210\u53d1\u9001\u3002<\/p>\n\n\n\n\u6a21\u5757\u901a\u8fc7\u53c2\u6570 CLK_FREQ<\/code> \u548c BAUD_RATE<\/code> \u63a7\u5236\u6ce2\u7279\u7387\uff0c\u5185\u90e8\u8ba1\u7b97\u6bcf\u4e2a\u4f4d\u7684\u53d1\u9001\u5468\u671f BAUD_TICK = CLK_FREQ \/ BAUD_RATE<\/code>\u3002\u53ef\u5728\u4f8b\u5316\u6a21\u5757\u65f6\u4fee\u6539\u8fd9\u4e24\u4e2a\u53c2\u6570\u4ee5\u9002\u914d\u4e0d\u540c\u7684\u7cfb\u7edf\u65f6\u949f\u548c\u4e32\u53e3\u6ce2\u7279\u7387\u3002<\/strong><\/p>\n\n\n\nc) \u521b\u5efa\u4e32\u53e3\u63a5\u6536\u6a21\u5757( uart_rx.v<\/code><\/strong> \uff09<\/p>\n\n\n\n\u529f\u80fd\uff1a\u5bf9\u8f93\u5165\u7684 rx \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff0c\u7136\u540e\u8f93\u51fa\u8fd9\u4e2a\u63d0\u53d6\u5230\u76848\u4f4d\u6570\u636e\uff08rx_data<\/code>\uff09\uff0c\u5e76\u62c9\u9ad8rx_done<\/code>\u4fe1\u53f7\uff08\u4e00\u4e2a\u5468\u671f\uff09\u4ee5\u8868\u793a\u63a5\u6536\u5b8c\u6210\u3002<\/p>\n\n\n\nmodule uart_rx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire rx,
output reg [7:0] rx_data,
output reg rx_done
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
localparam HALF_BAUD = BAUD_TICK \/ 2;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_cnt = 0;
reg [7:0] rx_shift = 0;
reg [1:0] rx_sync = 2'b11;
reg rx_busy = 0;
reg start_edge = 0;
always @(posedge clk) begin
rx_sync <= {rx_sync[0], rx};
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
start_edge <= 0;
else
start_edge <= (!rx_busy && rx_sync == 2'b10);
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_busy <= 0;
rx_done <= 0;
baud_cnt <= 0;
bit_cnt <= 0;
rx_shift <= 0;
rx_data <= 0;
end
else begin
rx_done <= 0;
if (start_edge) begin
rx_busy <= 1;
baud_cnt <= 0;
bit_cnt <= 0;
end
if (rx_busy) begin
baud_cnt <= baud_cnt + 1;
if ((bit_cnt == 0 && baud_cnt == HALF_BAUD) || (bit_cnt > 0 && baud_cnt == BAUD_TICK)) begin
baud_cnt <= 0;
bit_cnt <= bit_cnt + 1;
if (bit_cnt >= 1 && bit_cnt <= 8) begin
rx_shift[bit_cnt - 1] <= rx_sync[1];
end
if (bit_cnt == 9) begin
rx_data <= rx_shift;
rx_done <= 1;
rx_busy <= 0;
end
end
end
end
end
endmodule<\/pre>\n\n\n\n\u7531\u4e8e rx<\/code> \u5bf9\u4e8e\u7cfb\u7edf\u6765\u8bf4\u662f\u5f02\u6b65\u4fe1\u53f7\uff0c\u6240\u4ee5\u8fd9\u91cc\u9996\u5148\u5bf9\u8f93\u5165\u4fe1\u53f7 rx<\/code> \u8fdb\u884c\u540c\u6b65\u3002\u4f7f\u7528\u4e86 rx_sync<\/code> \u5bc4\u5b58\u5668\u8fdb\u884c\u540c\u6b65\uff0c\u4ee5\u6d88\u9664\u65f6\u949f\u57df\u4ea4\u53c9\u53ef\u80fd\u5e26\u6765\u7684\u95ee\u9898\u3002\u901a\u8fc7 start_edge<\/code> \u4fe1\u53f7\u68c0\u6d4b UART \u6570\u636e\u7684\u8d77\u59cb\u8fb9\u6cbf\uff08\u4e0b\u964d\u6cbf\uff09\uff0c\u4ee5\u786e\u5b9a\u63a5\u6536\u6570\u636e\u7684\u5f00\u59cb\u4f4d\u7f6e\u3002<\/p>\n\n\n\n\u5f53\u6570\u636e\u5f00\u59cb\u63a5\u6536\u540e\uff0c\u6a21\u5757\u4f1a\u6839\u636e\u6ce2\u7279\u7387\u8bbe\u7f6e\u7684\u65f6\u95f4\u95f4\u9694\uff08\u901a\u8fc7 baud_cnt<\/code> \u8ba1\u6570\u5668\uff09\u6765\u6309\u4f4d\u63a5\u6536\u6570\u636e\u3002\u6bcf\u5f53\u63a5\u6536\u5230\u4e00\u4f4d\u6570\u636e\uff0c\u5c31\u4f1a\u5c06\u6570\u636e\u5b58\u50a8\u5230\u4e00\u4e2a\u5bc4\u5b58\u5668 rx_shift<\/code> \u4e2d\uff0c\u76f4\u5230\u63a5\u6536\u5230 8 \u4f4d\u6570\u636e\uff08\u5373\u4e00\u4e2a\u5b8c\u6574\u7684\u5b57\u8282\uff09\u3002\u4e00\u65e6\u63a5\u6536\u5b8c\u4e00\u4e2a\u5b57\u8282\uff0c\u5c31\u5c06\u8fd9\u4e2a\u5b57\u8282\u8f93\u51fa\u5230 rx_data<\/code>\uff0c\u5e76\u901a\u8fc7 rx_done<\/code> \u4fe1\u53f7\u544a\u77e5\u5916\u90e8\uff0c\u6570\u636e\u5df2\u7ecf\u51c6\u5907\u597d\u3002<\/p>\n\n\n\n\u53e6\u5916\u6570\u636e\u7684\u91c7\u6837\u662f\u5728\u6570\u636e\u7684\u4e2d\u5fc3\u70b9\u4f4d\u7f6e\u8fdb\u884c\u91c7\u6837\u7684\uff08\u5f53 baud_cnt<\/code> \u8ba1\u6570\u5230HALF_BAUD<\/code>\u65f6\u8fdb\u884c\u91c7\u6837\uff0c\u5373\u6355\u6349\u6570\u636e\u4f4d\u7684\u4e2d\u5fc3\u70b9\uff09\u786e\u4fdd\u6570\u636e\u5728\u6700\u7a33\u5b9a\u7684\u65f6\u523b\u88ab\u91c7\u6837\uff0c\u4ee5\u4fdd\u8bc1\u4e86\u6570\u636e\u63a5\u6536\u7684\u53ef\u9760\u6027\u548c\u7cbe\u5ea6\u3002<\/p>\n\n\n\nd\uff09\u6700\u540e\u518d\u589e\u52a0\u7ea6\u675f\u6587\u4ef6\uff0c\u5bf9\u7ba1\u811a\u8fdb\u884c\u5b9a\u4e49 \uff08PIN.XDC\uff09<\/strong><\/p>\n\n\n\n# Clock Constraints
set_property PACKAGE_PIN Y18 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
# Define the clock period for 50 MHz
create_clock -period 20.000 -name CLK -waveform {0.000 10.000} [get_ports CLK]
# Reset Constraints (active-low reset)
set_property PACKAGE_PIN T20 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
# UART Constraints
set_property PACKAGE_PIN P14 [get_ports rx]
set_property PACKAGE_PIN R14 [get_ports tx]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]<\/pre>\n\n\n\n\u4e09\u3001\u7f16\u8bd1\u7efc\u5408\uff0c\u5e76\u8fd0\u884c\u4ee3\u7801<\/strong><\/h2>\n\n\n\n1\uff09\u5c06\u4e3b\u677f\u7684UART\u53e3\uff08TYPE C\u53e3\uff09\u7528\u6570\u636e\u7ebf\u4e0e\u7535\u8111\u8fdb\u884c\u8fde\u63a5 \u3002\uff08Smart Artix \u4e3b\u677f\u4e0b\u8f7d\u5668\u4e0eUART\u5171\u7528\u4e00\u4e2aTYPE C\u53e3\uff092\uff09\u5728\u7535\u8111\u7aef\u63d0\u524d\u6253\u5f00\u4e32\u53e3\u52a9\u624b\uff0c\u6ce2\u7279\u7387\u8bbe\u7f6e\u6210115200\uff0c\u5e76\u5f00\u542f\u4e32\u53e3\u529f\u80fd\u3002 3\uff09\u5728Vivado \u4e0a\u5bf9FPGA\u82af\u7247\u8fdb\u884cProgram\u3002<\/p>\n\n\n\n
\u6210\u529f\u540e\u53ef\u4ee5\u4ece\u4e32\u53e3\u52a9\u624b\u4e0a\u770b\u5230hellofpga.com\u7684\u5b57\u7b26\u5185\u5bb9\uff0c\u4e4b\u540e\u4e3b\u677f\u7cfb\u7edf\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff0c \u56de\u73af\u6a21\u5f0f\u4e0b\u6211\u4eec\u901a\u8fc7\u4e32\u53e3\u52a9\u624b\u5411\u4e3b\u677f\u53d1\u9001\u4efb\u4f55\u5185\u5bb9\uff0c \u4e3b\u677f\u90fd\u4f1a\u5c06\u89e3\u6790\u5230\u7684\u6570\u636e\u8fdb\u884c\u56de\u4f20\u5e76\u663e\u793a\u5728\u4e32\u53e3\u52a9\u624b\u7684\u63a5\u6536\u9875\u9762\uff0c\u5982\u4e0b\u56fe\u6240\u793a\uff0c\u8bc1\u660e\u6211\u4eec\u7684\u4e32\u53e3\u6a21\u5757\u5de5\u4f5c\u6210\u529f\u3002<\/p>\n\n\n\n
\u5907\u6ce8: \u7531\u4e8eFT\u82af\u7247\u4ef7\u683c\u6ce2\u52a8\u5389\u5bb3\uff0c\u6240\u4ee5\u4e3b\u677f\u5728\u8bbe\u8ba1\u4e0a\u517c\u5bb9\u4e86FT4232HL\u548cFT2232HL\u4e24\u4e2aJTAG\u82af\u7247\u578b\u53f7\uff0c\u5982\u679c\u4e3b\u677f\u662f\u8d34FT4232HL\uff0c\u90a3\u4e48\u63a5\u7535\u8111\u4e0a\u4f1a\u51fa\u73b03\u4e2a\u4e32\u53e3\uff08\u90fd\u662f\u53ef\u4ee5\u4f7f\u7528\u7684\uff09\uff0c\u5982\u679c\u4e3b\u677f\u4e0a\u8d34\u7684\u662fFT2232HL\uff0c\u90a3\u4e48\u4e32\u53e3\u53ea\u6709\u4e00\u8def\uff08\u9996\u6279\u4e3b\u677f\u8d34\u7684\u662fFT4232HL\uff09<\/strong><\/p>\n\n\n\n\u5982\u679c\u662fFT4232HL\u7684\u7248\u672c\uff0c\u5982\u679c\u4e32\u53e3\u6570\u636e\u6ca1\u6709\u6b63\u786e\u663e\u793a\uff0c\u8bf7\u5c1d\u8bd5\u5207\u63623\u4e2a\u4e32\u53e3\u4e2d\u7684\u53e6\u4e24\u4e2a\uff0c\u76f4\u5230\u6253\u5f00\u6b63\u786e\u7684\u4e32\u53e3\u7aef\u53f7\u4e3a\u6b62\u3002<\/strong><\/p>\n\n\n\n![\"\"](\"http:\/\/www.hellofpga.com\/wp-content\/uploads\/2025\/04\/image-11.png\")
<\/figure>\n\n\n\n\u4e0b\u5217\u662f\u672c\u6b21\u5b9e\u9a8c\u7684\u5b8c\u6574\u5de5\u7a0b\uff1a<\/strong><\/h2>\n\n\n\n
UART\u662f\u4e00\u79cd\u4e32\u884c\u901a\u4fe1\u534f\u8bae\uff0c\u7528\u4e8e\u5728\u8bbe\u5907\u4e4b\u95f4\u4f20\u8f93\u6570\u636e\u3002\u5b83\u901a\u5e38\u7528\u4e8e\u8fde\u63a5\u8ba1\u7b97\u673a\u4e0e\u5916\u90e8\u8bbe\u5907\uff08\u6bd4\u5982\u4f20\u611f\u5668\u3001\u663e\u793a\u5668\u3001\u6a21\u5757\u7b49\uff09\u3002<\/p>\n\n\n\n
UART\u4e0d\u50cf\u5176\u4ed6\u534f\u8bae\uff08\u6bd4\u5982SPI\u6216I2C\uff09\u9700\u8981\u540c\u6b65\u65f6\u949f\u4fe1\u53f7\uff0c\u56e0\u6b64\u88ab\u79f0\u4e3a\u5f02\u6b65\u534f\u8bae\u3002\u8fd9\u610f\u5473\u7740\u53d1\u9001\u548c\u63a5\u6536\u8bbe\u5907\u4e0d\u9700\u8981\u5171\u4eab\u540c\u6b65\u65f6\u949f\u3002\u6bcf\u4e2a\u8bbe\u5907\u6709\u81ea\u5df1\u7684\u65f6\u949f\uff0c\u5e76\u4e14\u901a\u8fc7\u8d77\u59cb\u4f4d\u6765\u540c\u6b65\u6570\u636e\u4f20\u8f93\u3002<\/p>\n\n\n\n
UART\u7684\u534f\u8bae\u6784\u6210\uff1a<\/strong><\/h3>\n\n\n\n\n- \u8d77\u59cb\u4f4d\uff08Start Bit\uff09<\/strong>\uff1a\u6307\u793a\u6570\u636e\u4f20\u8f93\u5f00\u59cb\u7684\u4f4d\u3002\u5b83\u662f\u903b\u8f91\u4f4e\u7535\u5e73\uff080\uff09\uff08\u603b\u7ebf\u7a7a\u95f2\u65f6\u4e3a\u9ad8\u7535\u5e73\uff0c\u6240\u4ee5\u5f00\u59cb\u901a\u4fe1\u65f6\u5148\u53d1\u9001\u4e00\u4e2a\u533a\u522b\u4e8e\u7a7a\u95f2\u72b6\u6001\u7684\u4fe1\u53f7\uff0c\u8d77\u59cb\u4f4d\u4e5f\u4f5c\u65f6\u949f\u540c\u6b65\u7528\uff09<\/li>\n\n\n\n
- \u6570\u636e\u4f4d\uff08Data Bits\uff09<\/strong>\uff1a\u5305\u542b\u8981\u4f20\u8f93\u7684\u6570\u636e\uff0c\u901a\u5e38\u4e3a8\u4f4d\uff0c\u5148\u53d1\u9001\u6570\u636e\u7684\u6700\u4f4e\u4f4d\uff0c\u6700\u540e\u53d1\u9001\u6570\u636e\u7684\u6700\u9ad8\u4f4d\uff0c<\/li>\n\n\n\n
- \u5947\u5076\u6821\u9a8c\u4f4d\uff08Parity Bit\uff09<\/strong>\uff08\u53ef\u9009\uff09\uff1a\u7528\u4e8e\u6570\u636e\u6821\u9a8c\uff0c\u6709\u5947\u5076\u4e24\u79cd\u7c7b\u578b\uff0c\u6709\u65f6\u7528\u4e8e\u68c0\u6d4b\u4f20\u8f93\u4e2d\u7684\u9519\u8bef\u3002<\/li>\n\n\n\n
- \u505c\u6b62\u4f4d\uff08Stop Bit\uff09<\/strong>\uff1a\u6807\u5fd7\u6570\u636e\u4f20\u8f93\u7ed3\u675f\u7684\u4f4d\uff0c\u901a\u5e38\u662f\u903b\u8f91\u9ad8\u7535\u5e73\uff081\uff09<\/li>\n\n\n\n
- \u7a7a\u95f2\u65f6\u6bb5<\/strong>\uff1aUART\u534f\u8bae\u89c4\u5b9a\uff0c\u5f53\u603b\u7ebf\u5904\u4e8e\u7a7a\u95f2\u72b6\u6001\u65f6\u4fe1\u53f7\u7ebf\u7684\u72b6\u6001\u4e3a\uff081\uff09<\/li>\n<\/ul>\n\n\n\n
\u4e5f\u5c31\u662f\u5982\u679c\u6211\u4eec\u89c2\u5bdfUART\u6ce2\u5f62\u53ef\u4ee5\u770b\u5230\u5728\u6ca1\u6709\u901a\u8baf\u7684\u65f6\u5019\uff0cUART\u4fe1\u53f7\u7ebf\u662f\u662f\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u5373\u7a7a\u95f2\u72b6\u6001\uff09\uff0c\u5f53\u4e00\u4e2a\u4e0b\u964d\u6cbf\u4e8b\u4ef6\u53d1\u751f\u65f6\uff0c\u6211\u4eec\u8ba4\u4e3a\u5c06\u8fdb\u884c\u4e00\u6b21\u6570\u636e\u7684\u4f20\u8f93\u3002<\/p>\n\n\n\n<\/figure>\n\n\n\n\u4e24\u4e2a\u8bbe\u5907\u8981\u7528UART\u8fdb\u884c\u901a\u8baf\uff0cTX\u548cRX\u4e24\u4e2a\u4fe1\u53f7\u7ebf\u662f\u9700\u8981\u4ea4\u53c9\u7684\uff0c\u9664\u4e86TX\u548cRX\u4fe1\u53f7\u5916\uff0c\u4e24\u4e2a\u8bbe\u5907\u95f4\u8fd8\u9700\u8981\u5171\u5730(GND)\u3002<\/p>\n\n\n\n<\/figure>\n\n\n\nUART \u901a\u8baf\u7535\u5e73<\/strong><\/h2>\n\n\n\n\n- UART\u7684\u7535\u5e73\uff0c\u5176\u5b9e\u662f\u6709\u4e24\u79cd\u89c4\u683c\u7684\uff0c\u4e24\u8005\u7535\u538b\u4e0d\u540c\uff0c\u903b\u8f91\u4e5f\u76f8\u53cd\uff0c\u4e0d\u80fd\u76f4\u63a5\u8fde\u63a5<\/strong>\n
\n- RS232 <\/strong>( \u00b112V, \u5176\u4e2d+12V\u4ee3\u8868\u903b\u8f911\uff0c-12V\u4ee3\u8868\u903b\u8f910) \u591a\u7528\u4e8e\u8001\u5f0f\u7535\u8111\u4e32\u53e3\u548c\u5de5\u4e1a\u8bbe\u5907\u7684\u901a\u8baf<\/li>\n\n\n\n
- TTL232<\/strong>\uff083.3V\/5V\u4ee3\u8868\u903b\u8f911\uff0c 0V\u4ee3\u8868\u903b\u8f910\uff09\u5e38\u7528\u4e8e\u5355\u7247\u673a\u3001\u5f00\u53d1\u677f\u7b49\u5d4c\u5165\u5f0f\u7cfb\u7edf<\/li>\n\n\n\n
- RS232\u548cTTL232\u53ef\u901a\u8fc7\u4e13\u7528\u82af\u7247\u8fdb\u884c\u8f6c\u6362\uff0c\u5982\uff08MAX232\u82af\u7247\u7b49\uff09<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n
\u4e8c\u3001\u5de5\u7a0b\u521b\u5efa\uff1a<\/strong><\/h2>\n\n\n\n\u5de5\u7a0b\u521b\u5efa\u7684\u8fc7\u7a0b\u53ef\u4ee5\u53c2\u8003\u5b9e\u9a8c\u4e00\u4e2d\u7684\u5185\u5bb9\uff0c\u8fd9\u91cc\u4e0d\u8be6\u7ec6\u63cf\u8ff0\u4e86\u3002<\/a>\u57fa\u4e8eSmart Artix \u7684FPGA\u5b9e\u9a8c\u4e00 \u7528FPGA\u8d44\u6e90\u70b9\u4eae\u4e00\u4e2aLED\uff08\u5b8c\u6574\u56fe\u6587\uff09<\/a> (\u82af\u7247\u578b\u53f7\u9009XC7A50TFGG484-2)<\/strong><\/p>\n\n\n\n\u5b9e\u9a8c\u5185\u5bb9\uff1a<\/strong><\/h2>\n\n\n\n\n- \u672c\u6b21\u5b9e\u9a8c\u6211\u4eec\u5c06\u8bbe\u8ba1\u4e00\u4e2a\u7b80\u5355\u7684UART\u6a21\u5757\uff0c\u5177\u4f53\u529f\u80fd\u5982\u4e0b\uff1a<\/strong>\n
\n- \u4e0a\u7535\u540e\uff0c\u4e32\u53e3\u81ea\u52a8\u53d1\u9001\u5b57\u7b26\u4e32\uff1a
hellofpga.com<\/code><\/strong><\/li>\n\n\n\n- \u53d1\u9001\u5b8c\u6210\u540e\uff0c\u8fdb\u5165\u56de\u73af\u6a21\u5f0f<\/strong>\uff1a\u4e32\u53e3\u63a5\u6536\u7684\u6570\u636e\u76f4\u63a5\u539f\u6837\u8fd4\u56de\u53d1\u9001\uff08Loopback\uff09<\/li>\n\n\n\n
- \u4e32\u53e3\u6a21\u5757\u7cfb\u7edf\u65f6\u949f50M\uff0c\u6ce2\u7279\u7387115200\uff0c8 \u4f4d\u6570\u636e\uff0c\u65e0\u6821\u9a8c\uff0c1 \u4f4d\u505c\u6b62\u4f4d\uff088N1\uff09<\/li>\n<\/ul>\n<\/li>\n\n\n\n
- \u5de5\u7a0b\u5c06\u5206\u4e3a3\u4e2a\u6a21\u5757\u6765\u8fdb\u884c\u8bbe\u8ba1\uff1a<\/strong>\n
\n- \u9876\u5c42\u6a21\u5757
uart_top.v<\/code><\/strong>\uff08\u521d\u59cb\u5316\u65f6\u53d1\u9001\u5b57\u7b26\u4e32 \"hellofpga.com\"<\/code>\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff09<\/li>\n\n\n\n- \u4e32\u53e3\u53d1\u9001\u6a21\u5757
uart_tx.v<\/code><\/strong>\uff08\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff09<\/li>\n\n\n\n- \u4e32\u53e3\u63a5\u6536\u6a21\u5757
uart_rx.v<\/code><\/strong>\uff08\u5bf9\u8f93\u5165\u7684 RX \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff09<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\na) \u521b\u5efa\u4e00\u4e2a\u9876\u5c42\u6a21\u5757\uff08uart_top.v<\/code>\uff09<\/strong><\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_top(
input wire clk,
input wire rst_n,
input wire rx,
output wire tx
);
localparam INIT = 2'd0;
localparam SENDING = 2'd1;
localparam LOOP = 2'd2;
reg [1:0] state = INIT;
reg start_tx = 0;
reg [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire rx_done;
reg [3:0] send_index = 0;
reg [7:0] send_buf [12:0];
reg [7:0] tx_buf;
reg tx_req;
initial begin
send_buf[0] = \"h\";
send_buf[1] = \"e\";
send_buf[2] = \"l\";
send_buf[3] = \"l\";
send_buf[4] = \"o\";
send_buf[5] = \"f\";
send_buf[6] = \"p\";
send_buf[7] = \"g\";
send_buf[8] = \"a\";
send_buf[9] = \".\";
send_buf[10] = \"c\";
send_buf[11] = \"o\";
send_buf[12] = \"m\";
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= INIT;
send_index <= 0;
start_tx <= 0;
tx_req <= 0;
end else begin
case (state)
INIT: begin
state <= SENDING;
send_index <= 0;
end
SENDING: begin
if (!tx_busy && !start_tx && send_index < 13) begin
tx_data <= send_buf[send_index];
start_tx <= 1;
send_index <= send_index + 1;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end else if (send_index >= 13 && !tx_busy) begin
state <= LOOP;
end
end
LOOP: begin
if (rx_done && !tx_req) begin
tx_buf <= rx_data;
tx_req <= 1;
end
if (tx_req && !tx_busy && !start_tx) begin
tx_data <= tx_buf;
start_tx <= 1;
tx_req <= 0;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end
end
endcase
end
end
uart_tx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_tx (
.clk(clk),
.rst_n(rst_n),
.tx_data(tx_data),
.tx_start(start_tx),
.tx(tx),
.tx_busy(tx_busy)
);
uart_rx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_rx (
.clk(clk),
.rst_n(rst_n),
.rx(rx),
.rx_data(rx_data),
.rx_done(rx_done)
);
endmodule<\/pre>\n\n\n\nUART \u9876\u5c42\u6a21\u5757\u5728\u7cfb\u7edf\u542f\u52a8\u65f6\uff0c\u4f1a\u5148\u901a\u8fc7\u4e32\u53e3\u53d1\u9001\u4e00\u4e32\u5b57\u7b26\u4e32 \u201chellofpga.com\u201d\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\u3002\u6240\u8c13\u56de\u73af\u6a21\u5f0f\uff0c\u5c31\u662f\u6536\u5230\u4ec0\u4e48\u6570\u636e\uff0c\u5c31\u7acb\u5373\u4ece TX \u53d1\u56de\u53bb\uff0c\u5b9e\u73b0 UART \u7684\u6570\u636e\u56de\u9001\u529f\u80fd\uff0c\u65b9\u4fbf\u6d4b\u8bd5\u4e32\u53e3\u662f\u5426\u6b63\u5e38\u3002<\/p>\n\n\n\n
\u6574\u4e2a\u6a21\u5757\u5206\u4e3a\u4e09\u4e2a\u72b6\u6001\uff1a\u521d\u59cb\u5316\uff08INIT\uff09\u3001\u53d1\u9001\u56fa\u5b9a\u5b57\u7b26\u4e32\uff08SENDING\uff09\u548c\u56de\u73af\uff08LOOP\uff09\u3002\u4e3a\u907f\u514d\u53d1\u9001\u51b2\u7a81\uff0c\u56de\u73af\u90e8\u5206\u52a0\u5165\u4e86\u4e00\u4e2a\u53d1\u9001\u8bf7\u6c42\u6807\u5fd7 tx_req<\/code>\uff0c\u786e\u4fdd\u63a5\u6536\u6570\u636e\u540e\u4e0d\u4f1a\u4e22\u5305\u3002\u53d1\u9001\u548c\u63a5\u6536\u7684\u6ce2\u7279\u7387\u3001\u65f6\u949f\u9891\u7387\u90fd\u53ef\u901a\u8fc7\u53c2\u6570\u914d\u7f6e\uff0c\u4fbf\u4e8e\u7075\u6d3b\u4fee\u6539\u3002\uff08tx_req<\/code> \u662f\u4e00\u4e2a \u201c\u53d1\u9001\u51c6\u5907\u6807\u5fd7\u201d<\/strong>\uff0c\u8868\u793a\u5df2\u7ecf\u6536\u5230\u6570\u636e\u4f46\u8fd8\u6ca1\u53d1\u9001\u51fa\u53bb\uff0c\u7b49\u5230\u53d1\u9001\u6a21\u5757\u7a7a\u95f2\u65f6\u518d\u542f\u52a8\u53d1\u9001\uff0c\u9632\u6b62\u6570\u636e\u51b2\u7a81\u6216\u9057\u6f0f\uff09<\/p>\n\n\n\nb) \u521b\u5efa\u4e32\u53e3\u53d1\u9001\u6a21\u5757 (uart_tx.v<\/code><\/strong>)<\/p>\n\n\n\n\u529f\u80fd\uff1a\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff0c\uff08tx_start<\/code> \u62c9\u9ad8\u5f00\u59cb\u53d1\u9001\uff0c\u53d1\u9001\u671f\u95f4tx_busy<\/code> \u4e3a\u9ad8\u8868\u793a\u5f53\u524d\u6b63\u5728\u53d1\u9001\uff09<\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_tx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire [7:0] tx_data,
input wire tx_start,
output reg tx,
output reg tx_busy
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_idx = 0;
reg [9:0] tx_shift = 10'b1111111111;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx <= 1;
tx_busy <= 0;
baud_cnt <= 0;
bit_idx <= 0;
tx_shift <= 10'b1111111111;
end
else begin
if (tx_start && !tx_busy) begin
tx_shift <= {1'b1, tx_data, 1'b0};
tx_busy <= 1;
baud_cnt <= 0;
bit_idx <= 0;
end
else if (tx_busy) begin
if (baud_cnt == BAUD_TICK - 1) begin
baud_cnt <= 0;
tx <= tx_shift[bit_idx];
bit_idx <= bit_idx + 1;
if (bit_idx == 9) begin
tx_busy <= 0;
tx <= 1;
end
end
else begin
baud_cnt <= baud_cnt + 1;
end
end
end
end
endmodule<\/pre>\n\n\n\n\u5f53 tx_start<\/code> \u4fe1\u53f7\u4e3a\u9ad8\u5e76\u4e14\u5f53\u524d\u53d1\u9001\u5668\u7a7a\u95f2\u65f6\uff0c\u6a21\u5757\u5c06\u6570\u636e\u6253\u5305\u6210 10 \u4f4d\u53d1\u9001\u5e27\uff08\u8d77\u59cb\u4f4d + \u6570\u636e + \u505c\u6b62\u4f4d\uff09\uff0c\u5e76\u5f00\u59cb\u4ee5\u56fa\u5b9a\u6ce2\u7279\u7387\uff08\u7531 CLK_FREQ<\/code> \u4e0e BAUD_RATE<\/code> \u53c2\u6570\u51b3\u5b9a\uff09\u9010\u4f4d\u8f93\u51fa\u5230 tx<\/code>\u3002\u53d1\u9001\u8fc7\u7a0b\u4e2d\uff0ctx_busy<\/code> \u4f1a\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u8868\u793a\u53d1\u9001\u5668\u6b63\u5fd9\uff09\uff0c\u76f4\u5230\u6240\u6709\u4f4d\u5b8c\u6210\u53d1\u9001\u3002<\/p>\n\n\n\n\u6a21\u5757\u901a\u8fc7\u53c2\u6570 CLK_FREQ<\/code> \u548c BAUD_RATE<\/code> \u63a7\u5236\u6ce2\u7279\u7387\uff0c\u5185\u90e8\u8ba1\u7b97\u6bcf\u4e2a\u4f4d\u7684\u53d1\u9001\u5468\u671f BAUD_TICK = CLK_FREQ \/ BAUD_RATE<\/code>\u3002\u53ef\u5728\u4f8b\u5316\u6a21\u5757\u65f6\u4fee\u6539\u8fd9\u4e24\u4e2a\u53c2\u6570\u4ee5\u9002\u914d\u4e0d\u540c\u7684\u7cfb\u7edf\u65f6\u949f\u548c\u4e32\u53e3\u6ce2\u7279\u7387\u3002<\/strong><\/p>\n\n\n\nc) \u521b\u5efa\u4e32\u53e3\u63a5\u6536\u6a21\u5757( uart_rx.v<\/code><\/strong> \uff09<\/p>\n\n\n\n\u529f\u80fd\uff1a\u5bf9\u8f93\u5165\u7684 rx \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff0c\u7136\u540e\u8f93\u51fa\u8fd9\u4e2a\u63d0\u53d6\u5230\u76848\u4f4d\u6570\u636e\uff08rx_data<\/code>\uff09\uff0c\u5e76\u62c9\u9ad8rx_done<\/code>\u4fe1\u53f7\uff08\u4e00\u4e2a\u5468\u671f\uff09\u4ee5\u8868\u793a\u63a5\u6536\u5b8c\u6210\u3002<\/p>\n\n\n\nmodule uart_rx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire rx,
output reg [7:0] rx_data,
output reg rx_done
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
localparam HALF_BAUD = BAUD_TICK \/ 2;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_cnt = 0;
reg [7:0] rx_shift = 0;
reg [1:0] rx_sync = 2'b11;
reg rx_busy = 0;
reg start_edge = 0;
always @(posedge clk) begin
rx_sync <= {rx_sync[0], rx};
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
start_edge <= 0;
else
start_edge <= (!rx_busy && rx_sync == 2'b10);
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_busy <= 0;
rx_done <= 0;
baud_cnt <= 0;
bit_cnt <= 0;
rx_shift <= 0;
rx_data <= 0;
end
else begin
rx_done <= 0;
if (start_edge) begin
rx_busy <= 1;
baud_cnt <= 0;
bit_cnt <= 0;
end
if (rx_busy) begin
baud_cnt <= baud_cnt + 1;
if ((bit_cnt == 0 && baud_cnt == HALF_BAUD) || (bit_cnt > 0 && baud_cnt == BAUD_TICK)) begin
baud_cnt <= 0;
bit_cnt <= bit_cnt + 1;
if (bit_cnt >= 1 && bit_cnt <= 8) begin
rx_shift[bit_cnt - 1] <= rx_sync[1];
end
if (bit_cnt == 9) begin
rx_data <= rx_shift;
rx_done <= 1;
rx_busy <= 0;
end
end
end
end
end
endmodule<\/pre>\n\n\n\n\u7531\u4e8e rx<\/code> \u5bf9\u4e8e\u7cfb\u7edf\u6765\u8bf4\u662f\u5f02\u6b65\u4fe1\u53f7\uff0c\u6240\u4ee5\u8fd9\u91cc\u9996\u5148\u5bf9\u8f93\u5165\u4fe1\u53f7 rx<\/code> \u8fdb\u884c\u540c\u6b65\u3002\u4f7f\u7528\u4e86 rx_sync<\/code> \u5bc4\u5b58\u5668\u8fdb\u884c\u540c\u6b65\uff0c\u4ee5\u6d88\u9664\u65f6\u949f\u57df\u4ea4\u53c9\u53ef\u80fd\u5e26\u6765\u7684\u95ee\u9898\u3002\u901a\u8fc7 start_edge<\/code> \u4fe1\u53f7\u68c0\u6d4b UART \u6570\u636e\u7684\u8d77\u59cb\u8fb9\u6cbf\uff08\u4e0b\u964d\u6cbf\uff09\uff0c\u4ee5\u786e\u5b9a\u63a5\u6536\u6570\u636e\u7684\u5f00\u59cb\u4f4d\u7f6e\u3002<\/p>\n\n\n\n\u5f53\u6570\u636e\u5f00\u59cb\u63a5\u6536\u540e\uff0c\u6a21\u5757\u4f1a\u6839\u636e\u6ce2\u7279\u7387\u8bbe\u7f6e\u7684\u65f6\u95f4\u95f4\u9694\uff08\u901a\u8fc7 baud_cnt<\/code> \u8ba1\u6570\u5668\uff09\u6765\u6309\u4f4d\u63a5\u6536\u6570\u636e\u3002\u6bcf\u5f53\u63a5\u6536\u5230\u4e00\u4f4d\u6570\u636e\uff0c\u5c31\u4f1a\u5c06\u6570\u636e\u5b58\u50a8\u5230\u4e00\u4e2a\u5bc4\u5b58\u5668 rx_shift<\/code> \u4e2d\uff0c\u76f4\u5230\u63a5\u6536\u5230 8 \u4f4d\u6570\u636e\uff08\u5373\u4e00\u4e2a\u5b8c\u6574\u7684\u5b57\u8282\uff09\u3002\u4e00\u65e6\u63a5\u6536\u5b8c\u4e00\u4e2a\u5b57\u8282\uff0c\u5c31\u5c06\u8fd9\u4e2a\u5b57\u8282\u8f93\u51fa\u5230 rx_data<\/code>\uff0c\u5e76\u901a\u8fc7 rx_done<\/code> \u4fe1\u53f7\u544a\u77e5\u5916\u90e8\uff0c\u6570\u636e\u5df2\u7ecf\u51c6\u5907\u597d\u3002<\/p>\n\n\n\n\u53e6\u5916\u6570\u636e\u7684\u91c7\u6837\u662f\u5728\u6570\u636e\u7684\u4e2d\u5fc3\u70b9\u4f4d\u7f6e\u8fdb\u884c\u91c7\u6837\u7684\uff08\u5f53 baud_cnt<\/code> \u8ba1\u6570\u5230HALF_BAUD<\/code>\u65f6\u8fdb\u884c\u91c7\u6837\uff0c\u5373\u6355\u6349\u6570\u636e\u4f4d\u7684\u4e2d\u5fc3\u70b9\uff09\u786e\u4fdd\u6570\u636e\u5728\u6700\u7a33\u5b9a\u7684\u65f6\u523b\u88ab\u91c7\u6837\uff0c\u4ee5\u4fdd\u8bc1\u4e86\u6570\u636e\u63a5\u6536\u7684\u53ef\u9760\u6027\u548c\u7cbe\u5ea6\u3002<\/p>\n\n\n\nd\uff09\u6700\u540e\u518d\u589e\u52a0\u7ea6\u675f\u6587\u4ef6\uff0c\u5bf9\u7ba1\u811a\u8fdb\u884c\u5b9a\u4e49 \uff08PIN.XDC\uff09<\/strong><\/p>\n\n\n\n# Clock Constraints
set_property PACKAGE_PIN Y18 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
# Define the clock period for 50 MHz
create_clock -period 20.000 -name CLK -waveform {0.000 10.000} [get_ports CLK]
# Reset Constraints (active-low reset)
set_property PACKAGE_PIN T20 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
# UART Constraints
set_property PACKAGE_PIN P14 [get_ports rx]
set_property PACKAGE_PIN R14 [get_ports tx]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]<\/pre>\n\n\n\n\u4e09\u3001\u7f16\u8bd1\u7efc\u5408\uff0c\u5e76\u8fd0\u884c\u4ee3\u7801<\/strong><\/h2>\n\n\n\n1\uff09\u5c06\u4e3b\u677f\u7684UART\u53e3\uff08TYPE C\u53e3\uff09\u7528\u6570\u636e\u7ebf\u4e0e\u7535\u8111\u8fdb\u884c\u8fde\u63a5 \u3002\uff08Smart Artix \u4e3b\u677f\u4e0b\u8f7d\u5668\u4e0eUART\u5171\u7528\u4e00\u4e2aTYPE C\u53e3\uff092\uff09\u5728\u7535\u8111\u7aef\u63d0\u524d\u6253\u5f00\u4e32\u53e3\u52a9\u624b\uff0c\u6ce2\u7279\u7387\u8bbe\u7f6e\u6210115200\uff0c\u5e76\u5f00\u542f\u4e32\u53e3\u529f\u80fd\u3002 3\uff09\u5728Vivado \u4e0a\u5bf9FPGA\u82af\u7247\u8fdb\u884cProgram\u3002<\/p>\n\n\n\n
\u6210\u529f\u540e\u53ef\u4ee5\u4ece\u4e32\u53e3\u52a9\u624b\u4e0a\u770b\u5230hellofpga.com\u7684\u5b57\u7b26\u5185\u5bb9\uff0c\u4e4b\u540e\u4e3b\u677f\u7cfb\u7edf\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff0c \u56de\u73af\u6a21\u5f0f\u4e0b\u6211\u4eec\u901a\u8fc7\u4e32\u53e3\u52a9\u624b\u5411\u4e3b\u677f\u53d1\u9001\u4efb\u4f55\u5185\u5bb9\uff0c \u4e3b\u677f\u90fd\u4f1a\u5c06\u89e3\u6790\u5230\u7684\u6570\u636e\u8fdb\u884c\u56de\u4f20\u5e76\u663e\u793a\u5728\u4e32\u53e3\u52a9\u624b\u7684\u63a5\u6536\u9875\u9762\uff0c\u5982\u4e0b\u56fe\u6240\u793a\uff0c\u8bc1\u660e\u6211\u4eec\u7684\u4e32\u53e3\u6a21\u5757\u5de5\u4f5c\u6210\u529f\u3002<\/p>\n\n\n\n
\u5907\u6ce8: \u7531\u4e8eFT\u82af\u7247\u4ef7\u683c\u6ce2\u52a8\u5389\u5bb3\uff0c\u6240\u4ee5\u4e3b\u677f\u5728\u8bbe\u8ba1\u4e0a\u517c\u5bb9\u4e86FT4232HL\u548cFT2232HL\u4e24\u4e2aJTAG\u82af\u7247\u578b\u53f7\uff0c\u5982\u679c\u4e3b\u677f\u662f\u8d34FT4232HL\uff0c\u90a3\u4e48\u63a5\u7535\u8111\u4e0a\u4f1a\u51fa\u73b03\u4e2a\u4e32\u53e3\uff08\u90fd\u662f\u53ef\u4ee5\u4f7f\u7528\u7684\uff09\uff0c\u5982\u679c\u4e3b\u677f\u4e0a\u8d34\u7684\u662fFT2232HL\uff0c\u90a3\u4e48\u4e32\u53e3\u53ea\u6709\u4e00\u8def\uff08\u9996\u6279\u4e3b\u677f\u8d34\u7684\u662fFT4232HL\uff09<\/strong><\/p>\n\n\n\n\u5982\u679c\u662fFT4232HL\u7684\u7248\u672c\uff0c\u5982\u679c\u4e32\u53e3\u6570\u636e\u6ca1\u6709\u6b63\u786e\u663e\u793a\uff0c\u8bf7\u5c1d\u8bd5\u5207\u63623\u4e2a\u4e32\u53e3\u4e2d\u7684\u53e6\u4e24\u4e2a\uff0c\u76f4\u5230\u6253\u5f00\u6b63\u786e\u7684\u4e32\u53e3\u7aef\u53f7\u4e3a\u6b62\u3002<\/strong><\/p>\n\n\n\n<\/figure>\n\n\n\n\u4e0b\u5217\u662f\u672c\u6b21\u5b9e\u9a8c\u7684\u5b8c\u6574\u5de5\u7a0b\uff1a<\/strong><\/h2>\n\n\n\n
\u4e5f\u5c31\u662f\u5982\u679c\u6211\u4eec\u89c2\u5bdfUART\u6ce2\u5f62\u53ef\u4ee5\u770b\u5230\u5728\u6ca1\u6709\u901a\u8baf\u7684\u65f6\u5019\uff0cUART\u4fe1\u53f7\u7ebf\u662f\u662f\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u5373\u7a7a\u95f2\u72b6\u6001\uff09\uff0c\u5f53\u4e00\u4e2a\u4e0b\u964d\u6cbf\u4e8b\u4ef6\u53d1\u751f\u65f6\uff0c\u6211\u4eec\u8ba4\u4e3a\u5c06\u8fdb\u884c\u4e00\u6b21\u6570\u636e\u7684\u4f20\u8f93\u3002<\/p>\n\n\n\n \u4e24\u4e2a\u8bbe\u5907\u8981\u7528UART\u8fdb\u884c\u901a\u8baf\uff0cTX\u548cRX\u4e24\u4e2a\u4fe1\u53f7\u7ebf\u662f\u9700\u8981\u4ea4\u53c9\u7684\uff0c\u9664\u4e86TX\u548cRX\u4fe1\u53f7\u5916\uff0c\u4e24\u4e2a\u8bbe\u5907\u95f4\u8fd8\u9700\u8981\u5171\u5730(GND)\u3002<\/p>\n\n\n\n \u5de5\u7a0b\u521b\u5efa\u7684\u8fc7\u7a0b\u53ef\u4ee5\u53c2\u8003\u5b9e\u9a8c\u4e00\u4e2d\u7684\u5185\u5bb9\uff0c\u8fd9\u91cc\u4e0d\u8be6\u7ec6\u63cf\u8ff0\u4e86\u3002<\/a>\u57fa\u4e8eSmart Artix \u7684FPGA\u5b9e\u9a8c\u4e00 \u7528FPGA\u8d44\u6e90\u70b9\u4eae\u4e00\u4e2aLED\uff08\u5b8c\u6574\u56fe\u6587\uff09<\/a> (\u82af\u7247\u578b\u53f7\u9009XC7A50TFGG484-2)<\/strong><\/p>\n\n\n\n a) \u521b\u5efa\u4e00\u4e2a\u9876\u5c42\u6a21\u5757\uff08 UART \u9876\u5c42\u6a21\u5757\u5728\u7cfb\u7edf\u542f\u52a8\u65f6\uff0c\u4f1a\u5148\u901a\u8fc7\u4e32\u53e3\u53d1\u9001\u4e00\u4e32\u5b57\u7b26\u4e32 \u201chellofpga.com\u201d\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\u3002\u6240\u8c13\u56de\u73af\u6a21\u5f0f\uff0c\u5c31\u662f\u6536\u5230\u4ec0\u4e48\u6570\u636e\uff0c\u5c31\u7acb\u5373\u4ece TX \u53d1\u56de\u53bb\uff0c\u5b9e\u73b0 UART \u7684\u6570\u636e\u56de\u9001\u529f\u80fd\uff0c\u65b9\u4fbf\u6d4b\u8bd5\u4e32\u53e3\u662f\u5426\u6b63\u5e38\u3002<\/p>\n\n\n\n \u6574\u4e2a\u6a21\u5757\u5206\u4e3a\u4e09\u4e2a\u72b6\u6001\uff1a\u521d\u59cb\u5316\uff08INIT\uff09\u3001\u53d1\u9001\u56fa\u5b9a\u5b57\u7b26\u4e32\uff08SENDING\uff09\u548c\u56de\u73af\uff08LOOP\uff09\u3002\u4e3a\u907f\u514d\u53d1\u9001\u51b2\u7a81\uff0c\u56de\u73af\u90e8\u5206\u52a0\u5165\u4e86\u4e00\u4e2a\u53d1\u9001\u8bf7\u6c42\u6807\u5fd7 b) \u521b\u5efa\u4e32\u53e3\u53d1\u9001\u6a21\u5757 ( \u529f\u80fd\uff1a\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff0c\uff08 \u5f53 \u6a21\u5757\u901a\u8fc7\u53c2\u6570 c) \u521b\u5efa\u4e32\u53e3\u63a5\u6536\u6a21\u5757( \u529f\u80fd\uff1a\u5bf9\u8f93\u5165\u7684 rx \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff0c\u7136\u540e\u8f93\u51fa\u8fd9\u4e2a\u63d0\u53d6\u5230\u76848\u4f4d\u6570\u636e\uff08 \u7531\u4e8e \u5f53\u6570\u636e\u5f00\u59cb\u63a5\u6536\u540e\uff0c\u6a21\u5757\u4f1a\u6839\u636e\u6ce2\u7279\u7387\u8bbe\u7f6e\u7684\u65f6\u95f4\u95f4\u9694\uff08\u901a\u8fc7 \u53e6\u5916\u6570\u636e\u7684\u91c7\u6837\u662f\u5728\u6570\u636e\u7684\u4e2d\u5fc3\u70b9\u4f4d\u7f6e\u8fdb\u884c\u91c7\u6837\u7684\uff08\u5f53 d\uff09\u6700\u540e\u518d\u589e\u52a0\u7ea6\u675f\u6587\u4ef6\uff0c\u5bf9\u7ba1\u811a\u8fdb\u884c\u5b9a\u4e49 \uff08PIN.XDC\uff09<\/strong><\/p>\n\n\n\n 1\uff09\u5c06\u4e3b\u677f\u7684UART\u53e3\uff08TYPE C\u53e3\uff09\u7528\u6570\u636e\u7ebf\u4e0e\u7535\u8111\u8fdb\u884c\u8fde\u63a5 \u3002\uff08Smart Artix \u4e3b\u677f\u4e0b\u8f7d\u5668\u4e0eUART\u5171\u7528\u4e00\u4e2aTYPE C\u53e3\uff092\uff09\u5728\u7535\u8111\u7aef\u63d0\u524d\u6253\u5f00\u4e32\u53e3\u52a9\u624b\uff0c\u6ce2\u7279\u7387\u8bbe\u7f6e\u6210115200\uff0c\u5e76\u5f00\u542f\u4e32\u53e3\u529f\u80fd\u3002 3\uff09\u5728Vivado \u4e0a\u5bf9FPGA\u82af\u7247\u8fdb\u884cProgram\u3002<\/p>\n\n\n\n \u6210\u529f\u540e\u53ef\u4ee5\u4ece\u4e32\u53e3\u52a9\u624b\u4e0a\u770b\u5230hellofpga.com\u7684\u5b57\u7b26\u5185\u5bb9\uff0c\u4e4b\u540e\u4e3b\u677f\u7cfb\u7edf\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff0c \u56de\u73af\u6a21\u5f0f\u4e0b\u6211\u4eec\u901a\u8fc7\u4e32\u53e3\u52a9\u624b\u5411\u4e3b\u677f\u53d1\u9001\u4efb\u4f55\u5185\u5bb9\uff0c \u4e3b\u677f\u90fd\u4f1a\u5c06\u89e3\u6790\u5230\u7684\u6570\u636e\u8fdb\u884c\u56de\u4f20\u5e76\u663e\u793a\u5728\u4e32\u53e3\u52a9\u624b\u7684\u63a5\u6536\u9875\u9762\uff0c\u5982\u4e0b\u56fe\u6240\u793a\uff0c\u8bc1\u660e\u6211\u4eec\u7684\u4e32\u53e3\u6a21\u5757\u5de5\u4f5c\u6210\u529f\u3002<\/p>\n\n\n\n \u5907\u6ce8: \u7531\u4e8eFT\u82af\u7247\u4ef7\u683c\u6ce2\u52a8\u5389\u5bb3\uff0c\u6240\u4ee5\u4e3b\u677f\u5728\u8bbe\u8ba1\u4e0a\u517c\u5bb9\u4e86FT4232HL\u548cFT2232HL\u4e24\u4e2aJTAG\u82af\u7247\u578b\u53f7\uff0c\u5982\u679c\u4e3b\u677f\u662f\u8d34FT4232HL\uff0c\u90a3\u4e48\u63a5\u7535\u8111\u4e0a\u4f1a\u51fa\u73b03\u4e2a\u4e32\u53e3\uff08\u90fd\u662f\u53ef\u4ee5\u4f7f\u7528\u7684\uff09\uff0c\u5982\u679c\u4e3b\u677f\u4e0a\u8d34\u7684\u662fFT2232HL\uff0c\u90a3\u4e48\u4e32\u53e3\u53ea\u6709\u4e00\u8def\uff08\u9996\u6279\u4e3b\u677f\u8d34\u7684\u662fFT4232HL\uff09<\/strong><\/p>\n\n\n\n \u5982\u679c\u662fFT4232HL\u7684\u7248\u672c\uff0c\u5982\u679c\u4e32\u53e3\u6570\u636e\u6ca1\u6709\u6b63\u786e\u663e\u793a\uff0c\u8bf7\u5c1d\u8bd5\u5207\u63623\u4e2a\u4e32\u53e3\u4e2d\u7684\u53e6\u4e24\u4e2a\uff0c\u76f4\u5230\u6253\u5f00\u6b63\u786e\u7684\u4e32\u53e3\u7aef\u53f7\u4e3a\u6b62\u3002<\/strong><\/p>\n\n\n\n<\/figure>\n\n\n\n<\/figure>\n\n\n\nUART \u901a\u8baf\u7535\u5e73<\/strong><\/h2>\n\n\n\n
\n
\n
\u4e8c\u3001\u5de5\u7a0b\u521b\u5efa\uff1a<\/strong><\/h2>\n\n\n\n
\u5b9e\u9a8c\u5185\u5bb9\uff1a<\/strong><\/h2>\n\n\n\n
\n
\n
hellofpga.com<\/code><\/strong><\/li>\n\n\n\n\n
uart_top.v<\/code><\/strong>\uff08\u521d\u59cb\u5316\u65f6\u53d1\u9001\u5b57\u7b26\u4e32 \"hellofpga.com\"<\/code>\uff0c\u53d1\u9001\u5b8c\u6210\u540e\u8fdb\u5165\u56de\u73af\u6a21\u5f0f\uff09<\/li>\n\n\n\nuart_tx.v<\/code><\/strong>\uff08\u5c06\u8f93\u5165\u7684 8 \u4f4d\u6570\u636e\u4ee5 UART \u683c\u5f0f\uff081 \u8d77\u59cb\u4f4d + 8 \u6570\u636e\u4f4d + 1 \u505c\u6b62\u4f4d\uff09\u4e32\u884c\u53d1\u9001\uff09<\/li>\n\n\n\nuart_rx.v<\/code><\/strong>\uff08\u5bf9\u8f93\u5165\u7684 RX \u4fe1\u53f7\u91c7\u6837\uff0c\u8bc6\u522b\u8d77\u59cb\u4f4d\uff0c\u63d0\u53d6 8 \u4f4d\u6570\u636e\uff09<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\nuart_top.v<\/code>\uff09<\/strong><\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_top(
input wire clk,
input wire rst_n,
input wire rx,
output wire tx
);
localparam INIT = 2'd0;
localparam SENDING = 2'd1;
localparam LOOP = 2'd2;
reg [1:0] state = INIT;
reg start_tx = 0;
reg [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire rx_done;
reg [3:0] send_index = 0;
reg [7:0] send_buf [12:0];
reg [7:0] tx_buf;
reg tx_req;
initial begin
send_buf[0] = \"h\";
send_buf[1] = \"e\";
send_buf[2] = \"l\";
send_buf[3] = \"l\";
send_buf[4] = \"o\";
send_buf[5] = \"f\";
send_buf[6] = \"p\";
send_buf[7] = \"g\";
send_buf[8] = \"a\";
send_buf[9] = \".\";
send_buf[10] = \"c\";
send_buf[11] = \"o\";
send_buf[12] = \"m\";
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= INIT;
send_index <= 0;
start_tx <= 0;
tx_req <= 0;
end else begin
case (state)
INIT: begin
state <= SENDING;
send_index <= 0;
end
SENDING: begin
if (!tx_busy && !start_tx && send_index < 13) begin
tx_data <= send_buf[send_index];
start_tx <= 1;
send_index <= send_index + 1;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end else if (send_index >= 13 && !tx_busy) begin
state <= LOOP;
end
end
LOOP: begin
if (rx_done && !tx_req) begin
tx_buf <= rx_data;
tx_req <= 1;
end
if (tx_req && !tx_busy && !start_tx) begin
tx_data <= tx_buf;
start_tx <= 1;
tx_req <= 0;
end else if (start_tx && tx_busy) begin
start_tx <= 0;
end
end
endcase
end
end
uart_tx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_tx (
.clk(clk),
.rst_n(rst_n),
.tx_data(tx_data),
.tx_start(start_tx),
.tx(tx),
.tx_busy(tx_busy)
);
uart_rx #(
.CLK_FREQ(50000000),
.BAUD_RATE(115200)
) u_rx (
.clk(clk),
.rst_n(rst_n),
.rx(rx),
.rx_data(rx_data),
.rx_done(rx_done)
);
endmodule<\/pre>\n\n\n\ntx_req<\/code>\uff0c\u786e\u4fdd\u63a5\u6536\u6570\u636e\u540e\u4e0d\u4f1a\u4e22\u5305\u3002\u53d1\u9001\u548c\u63a5\u6536\u7684\u6ce2\u7279\u7387\u3001\u65f6\u949f\u9891\u7387\u90fd\u53ef\u901a\u8fc7\u53c2\u6570\u914d\u7f6e\uff0c\u4fbf\u4e8e\u7075\u6d3b\u4fee\u6539\u3002\uff08tx_req<\/code> \u662f\u4e00\u4e2a \u201c\u53d1\u9001\u51c6\u5907\u6807\u5fd7\u201d<\/strong>\uff0c\u8868\u793a\u5df2\u7ecf\u6536\u5230\u6570\u636e\u4f46\u8fd8\u6ca1\u53d1\u9001\u51fa\u53bb\uff0c\u7b49\u5230\u53d1\u9001\u6a21\u5757\u7a7a\u95f2\u65f6\u518d\u542f\u52a8\u53d1\u9001\uff0c\u9632\u6b62\u6570\u636e\u51b2\u7a81\u6216\u9057\u6f0f\uff09<\/p>\n\n\n\nuart_tx.v<\/code><\/strong>)<\/p>\n\n\n\ntx_start<\/code> \u62c9\u9ad8\u5f00\u59cb\u53d1\u9001\uff0c\u53d1\u9001\u671f\u95f4tx_busy<\/code> \u4e3a\u9ad8\u8868\u793a\u5f53\u524d\u6b63\u5728\u53d1\u9001\uff09<\/p>\n\n\n\n`timescale 1ns \/ 1ps
module uart_tx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire [7:0] tx_data,
input wire tx_start,
output reg tx,
output reg tx_busy
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_idx = 0;
reg [9:0] tx_shift = 10'b1111111111;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx <= 1;
tx_busy <= 0;
baud_cnt <= 0;
bit_idx <= 0;
tx_shift <= 10'b1111111111;
end
else begin
if (tx_start && !tx_busy) begin
tx_shift <= {1'b1, tx_data, 1'b0};
tx_busy <= 1;
baud_cnt <= 0;
bit_idx <= 0;
end
else if (tx_busy) begin
if (baud_cnt == BAUD_TICK - 1) begin
baud_cnt <= 0;
tx <= tx_shift[bit_idx];
bit_idx <= bit_idx + 1;
if (bit_idx == 9) begin
tx_busy <= 0;
tx <= 1;
end
end
else begin
baud_cnt <= baud_cnt + 1;
end
end
end
end
endmodule<\/pre>\n\n\n\ntx_start<\/code> \u4fe1\u53f7\u4e3a\u9ad8\u5e76\u4e14\u5f53\u524d\u53d1\u9001\u5668\u7a7a\u95f2\u65f6\uff0c\u6a21\u5757\u5c06\u6570\u636e\u6253\u5305\u6210 10 \u4f4d\u53d1\u9001\u5e27\uff08\u8d77\u59cb\u4f4d + \u6570\u636e + \u505c\u6b62\u4f4d\uff09\uff0c\u5e76\u5f00\u59cb\u4ee5\u56fa\u5b9a\u6ce2\u7279\u7387\uff08\u7531 CLK_FREQ<\/code> \u4e0e BAUD_RATE<\/code> \u53c2\u6570\u51b3\u5b9a\uff09\u9010\u4f4d\u8f93\u51fa\u5230 tx<\/code>\u3002\u53d1\u9001\u8fc7\u7a0b\u4e2d\uff0ctx_busy<\/code> \u4f1a\u4fdd\u6301\u9ad8\u7535\u5e73\uff08\u8868\u793a\u53d1\u9001\u5668\u6b63\u5fd9\uff09\uff0c\u76f4\u5230\u6240\u6709\u4f4d\u5b8c\u6210\u53d1\u9001\u3002<\/p>\n\n\n\nCLK_FREQ<\/code> \u548c BAUD_RATE<\/code> \u63a7\u5236\u6ce2\u7279\u7387\uff0c\u5185\u90e8\u8ba1\u7b97\u6bcf\u4e2a\u4f4d\u7684\u53d1\u9001\u5468\u671f BAUD_TICK = CLK_FREQ \/ BAUD_RATE<\/code>\u3002\u53ef\u5728\u4f8b\u5316\u6a21\u5757\u65f6\u4fee\u6539\u8fd9\u4e24\u4e2a\u53c2\u6570\u4ee5\u9002\u914d\u4e0d\u540c\u7684\u7cfb\u7edf\u65f6\u949f\u548c\u4e32\u53e3\u6ce2\u7279\u7387\u3002<\/strong><\/p>\n\n\n\nuart_rx.v<\/code><\/strong> \uff09<\/p>\n\n\n\nrx_data<\/code>\uff09\uff0c\u5e76\u62c9\u9ad8rx_done<\/code>\u4fe1\u53f7\uff08\u4e00\u4e2a\u5468\u671f\uff09\u4ee5\u8868\u793a\u63a5\u6536\u5b8c\u6210\u3002<\/p>\n\n\n\nmodule uart_rx #(
parameter CLK_FREQ = 50000000,
parameter BAUD_RATE = 115200
)(
input wire clk,
input wire rst_n,
input wire rx,
output reg [7:0] rx_data,
output reg rx_done
);
localparam BAUD_TICK = CLK_FREQ \/ BAUD_RATE;
localparam HALF_BAUD = BAUD_TICK \/ 2;
reg [15:0] baud_cnt = 0;
reg [3:0] bit_cnt = 0;
reg [7:0] rx_shift = 0;
reg [1:0] rx_sync = 2'b11;
reg rx_busy = 0;
reg start_edge = 0;
always @(posedge clk) begin
rx_sync <= {rx_sync[0], rx};
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
start_edge <= 0;
else
start_edge <= (!rx_busy && rx_sync == 2'b10);
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_busy <= 0;
rx_done <= 0;
baud_cnt <= 0;
bit_cnt <= 0;
rx_shift <= 0;
rx_data <= 0;
end
else begin
rx_done <= 0;
if (start_edge) begin
rx_busy <= 1;
baud_cnt <= 0;
bit_cnt <= 0;
end
if (rx_busy) begin
baud_cnt <= baud_cnt + 1;
if ((bit_cnt == 0 && baud_cnt == HALF_BAUD) || (bit_cnt > 0 && baud_cnt == BAUD_TICK)) begin
baud_cnt <= 0;
bit_cnt <= bit_cnt + 1;
if (bit_cnt >= 1 && bit_cnt <= 8) begin
rx_shift[bit_cnt - 1] <= rx_sync[1];
end
if (bit_cnt == 9) begin
rx_data <= rx_shift;
rx_done <= 1;
rx_busy <= 0;
end
end
end
end
end
endmodule<\/pre>\n\n\n\nrx<\/code> \u5bf9\u4e8e\u7cfb\u7edf\u6765\u8bf4\u662f\u5f02\u6b65\u4fe1\u53f7\uff0c\u6240\u4ee5\u8fd9\u91cc\u9996\u5148\u5bf9\u8f93\u5165\u4fe1\u53f7 rx<\/code> \u8fdb\u884c\u540c\u6b65\u3002\u4f7f\u7528\u4e86 rx_sync<\/code> \u5bc4\u5b58\u5668\u8fdb\u884c\u540c\u6b65\uff0c\u4ee5\u6d88\u9664\u65f6\u949f\u57df\u4ea4\u53c9\u53ef\u80fd\u5e26\u6765\u7684\u95ee\u9898\u3002\u901a\u8fc7 start_edge<\/code> \u4fe1\u53f7\u68c0\u6d4b UART \u6570\u636e\u7684\u8d77\u59cb\u8fb9\u6cbf\uff08\u4e0b\u964d\u6cbf\uff09\uff0c\u4ee5\u786e\u5b9a\u63a5\u6536\u6570\u636e\u7684\u5f00\u59cb\u4f4d\u7f6e\u3002<\/p>\n\n\n\nbaud_cnt<\/code> \u8ba1\u6570\u5668\uff09\u6765\u6309\u4f4d\u63a5\u6536\u6570\u636e\u3002\u6bcf\u5f53\u63a5\u6536\u5230\u4e00\u4f4d\u6570\u636e\uff0c\u5c31\u4f1a\u5c06\u6570\u636e\u5b58\u50a8\u5230\u4e00\u4e2a\u5bc4\u5b58\u5668 rx_shift<\/code> \u4e2d\uff0c\u76f4\u5230\u63a5\u6536\u5230 8 \u4f4d\u6570\u636e\uff08\u5373\u4e00\u4e2a\u5b8c\u6574\u7684\u5b57\u8282\uff09\u3002\u4e00\u65e6\u63a5\u6536\u5b8c\u4e00\u4e2a\u5b57\u8282\uff0c\u5c31\u5c06\u8fd9\u4e2a\u5b57\u8282\u8f93\u51fa\u5230 rx_data<\/code>\uff0c\u5e76\u901a\u8fc7 rx_done<\/code> \u4fe1\u53f7\u544a\u77e5\u5916\u90e8\uff0c\u6570\u636e\u5df2\u7ecf\u51c6\u5907\u597d\u3002<\/p>\n\n\n\nbaud_cnt<\/code> \u8ba1\u6570\u5230HALF_BAUD<\/code>\u65f6\u8fdb\u884c\u91c7\u6837\uff0c\u5373\u6355\u6349\u6570\u636e\u4f4d\u7684\u4e2d\u5fc3\u70b9\uff09\u786e\u4fdd\u6570\u636e\u5728\u6700\u7a33\u5b9a\u7684\u65f6\u523b\u88ab\u91c7\u6837\uff0c\u4ee5\u4fdd\u8bc1\u4e86\u6570\u636e\u63a5\u6536\u7684\u53ef\u9760\u6027\u548c\u7cbe\u5ea6\u3002<\/p>\n\n\n\n# Clock Constraints
set_property PACKAGE_PIN Y18 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
# Define the clock period for 50 MHz
create_clock -period 20.000 -name CLK -waveform {0.000 10.000} [get_ports CLK]
# Reset Constraints (active-low reset)
set_property PACKAGE_PIN T20 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
# UART Constraints
set_property PACKAGE_PIN P14 [get_ports rx]
set_property PACKAGE_PIN R14 [get_ports tx]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]<\/pre>\n\n\n\n\u4e09\u3001\u7f16\u8bd1\u7efc\u5408\uff0c\u5e76\u8fd0\u884c\u4ee3\u7801<\/strong><\/h2>\n\n\n\n
<\/figure>\n\n\n\n\u4e0b\u5217\u662f\u672c\u6b21\u5b9e\u9a8c\u7684\u5b8c\u6574\u5de5\u7a0b\uff1a<\/strong><\/h2>\n\n\n\n